parameter: refine dual-core parameters on fpga platfrom

296bfcd2 · wangkaifan · 43bdc94d · 296bfcd2
隐藏空白更改
内联并排

Showing with 3 addition and 2 deletion

src/test/scala/top/XSSim.scala src/test/scala/top/XSSim.scala +3 -2

未找到文件。
--- a/src/test/scala/top/XSSim.scala
+++ b/src/test/scala/top/XSSim.scala
@@ -237,8 +237,9 @@ object TestMain extends App {
  val socArgs = args.filterNot(_ == "--with-dramsim3")
  Parameters.set(
    (socArgs.contains("--fpga-platform"), socArgs.contains("--dual-core"), socArgs.contains("--disable-log")) match {
-      case (true, _, _)          => Parameters()
-      case (false,  true,  true) => println("dual"); Parameters.simDualCoreParameters
+      case (true,  false, _)     => Parameters()
+      case (true,   true, _)     => Parameters.dualCoreParameters
+      case (false,  true,  true) => Parameters.simDualCoreParameters
      case (false, false,  true) => Parameters.simParameters
      case (false,  true, false) => Parameters.debugDualCoreParameters
      case (false, false, false) => Parameters.debugParameters