From 296bfcd2a1cff7bb0ba5656323c36b7865a28826 Mon Sep 17 00:00:00 2001
From: wangkaifan <wangkaifan@ict.ac.cn>
Date: Wed, 6 Jan 2021 15:39:02 +0800
Subject: [PATCH] parameter: refine dual-core parameters on fpga platfrom

---
 src/test/scala/top/XSSim.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/test/scala/top/XSSim.scala b/src/test/scala/top/XSSim.scala
index 58da18da2..9393cab16 100644
--- a/src/test/scala/top/XSSim.scala
+++ b/src/test/scala/top/XSSim.scala
@@ -237,8 +237,9 @@ object TestMain extends App {
   val socArgs = args.filterNot(_ == "--with-dramsim3")
   Parameters.set(
     (socArgs.contains("--fpga-platform"), socArgs.contains("--dual-core"), socArgs.contains("--disable-log")) match {
-      case (true, _, _)          => Parameters()
-      case (false,  true,  true) => println("dual"); Parameters.simDualCoreParameters
+      case (true,  false, _)     => Parameters()
+      case (true,   true, _)     => Parameters.dualCoreParameters
+      case (false,  true,  true) => Parameters.simDualCoreParameters
       case (false, false,  true) => Parameters.simParameters
       case (false,  true, false) => Parameters.debugDualCoreParameters
       case (false, false, false) => Parameters.debugParameters
-- 
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