StoreSet: add last fetched store table (LFST)

src/main/scala/xiangshan/Bundle.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan.backend.SelImm
 import xiangshan.backend.roq.RoqPtr
-import xiangshan.backend.decode.{ImmUnion, XDecode, MemPredParameters}
+import xiangshan.backend.decode.{ImmUnion, XDecode}
 import xiangshan.mem.{LqPtr, SqPtr}
 import xiangshan.frontend.PreDecodeInfoForDebug
 import xiangshan.frontend.PreDecodeInfo
@@ -23,7 +23,7 @@ import Chisel.experimental.chiselName
 import xiangshan.backend.ftq.FtqPtr
 
 // Fetch FetchWidth x 32-bit insts from Icache
-class FetchPacket extends XSBundle with MemPredParameters {
+class FetchPacket extends XSBundle {
   val instrs = Vec(PredictWidth, UInt(32.W))
   val mask = UInt(PredictWidth.W)
   val pdmask = UInt(PredictWidth.W)
@@ -171,7 +171,7 @@ class CfiUpdateInfo extends XSBundle with HasBPUParameter {
 }
 
 // Dequeue DecodeWidth insts from Ibuffer
-class CtrlFlow extends XSBundle with MemPredParameters {
+class CtrlFlow extends XSBundle  {
   val instr = UInt(32.W)
   val pc = UInt(VAddrBits.W)
   val foldpc = UInt(MemPredPCWidth.W)
@@ -180,6 +180,7 @@ class CtrlFlow extends XSBundle with MemPredParameters {
   val pd = new PreDecodeInfo
   val pred_taken = Bool()
   val crossPageIPFFix = Bool()
+  val storeSetHit = Bool() // inst has been allocated an store set
   val loadWaitBit = Bool() // load inst should not be executed until all former store addr calcuated
   val ftqPtr = new FtqPtr
   val ftqOffset = UInt(log2Up(PredictWidth).W)
@@ -301,6 +302,7 @@ class MicroOp extends CfCtrl {
   val roqIdx = new RoqPtr
   val lqIdx = new LqPtr
   val sqIdx = new SqPtr
+  val ssid = UInt(SSIDWidth.W)
   val diffTestDebugLrScValid = Bool()
   val debugInfo = new PerfDebugInfo
 }
@@ -456,7 +458,7 @@ class SfenceBundle extends XSBundle {
 }
 
 // Bundle for load violation predictor updating
-class MemPredUpdateReq extends XSBundle with MemPredParameters {
+class MemPredUpdateReq extends XSBundle  {
   val valid = Bool()
 
   // wait table update

src/main/scala/xiangshan/XSCore.scala

@@ -277,6 +277,17 @@ trait HasXSParameter {
       nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
     ),
   )
+
+  // load violation predict
+  val ResetTimeMax2Pow = 20 //1078576
+  val ResetTimeMin2Pow = 10 //1024
+  val MemPredPCWidth = log2Up(WaitTableSize)
+  // wait table parameters
+  val WaitTableSize = 1024
+  // store set parameters
+  val SSITSize = WaitTableSize
+  val LFSTSize = 32
+  val SSIDWidth = log2Up(LFSTSize)
 }
 
 trait HasXSLog {

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import utils._
 import xiangshan._
-import xiangshan.backend.decode.{DecodeStage, ImmUnion, MemPredParameters}
+import xiangshan.backend.decode.{DecodeStage, ImmUnion}
 import xiangshan.backend.rename.{BusyTable, Rename}
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
@@ -42,7 +42,7 @@ class CtrlToLsBlockIO extends XSBundle {
   val flush = Output(Bool())
 }
 
-class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper with MemPredParameters {
+class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper {
   val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt
   val io = IO(new Bundle() {
     val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput)))

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -16,6 +16,7 @@ import xiangshan.backend.issue.{ReservationStation}
 import xiangshan.backend.regfile.RfReadPort
 
 class LsBlockToCtrlIO extends XSBundle {
+  val stIn = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
   val stOut = Vec(exuParameters.StuCnt, ValidIO(new ExuOutput))
   val numExist = Vec(exuParameters.LsExuCnt, Output(UInt(log2Ceil(IssQueSize).W)))
   val replay = ValidIO(new Redirect)
@@ -286,6 +287,10 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     lsq.io.storeIssue(i).valid := rs.io.deq.valid
     lsq.io.storeIssue(i).bits := rs.io.deq.bits
 
+    // sync issue info to store set LFST
+    io.toCtrlBlock.stIn(i).valid := rs.io.deq.valid
+    io.toCtrlBlock.stIn(i).bits := rs.io.deq.bits
+
     io.toCtrlBlock.stOut(i).valid := stu.io.stout.valid
     io.toCtrlBlock.stOut(i).bits  := stu.io.stout.bits
     stu.io.stout.ready := true.B

src/main/scala/xiangshan/backend/decode/MemPredict.scala

-package xiangshan.backend.decode
-
-import chisel3._
-import chisel3.util._
-import xiangshan._
-import utils._
-
-trait MemPredParameters {
-  val ResetTimeMax2Pow = 20 //1078576
-  val ResetTimeMin2Pow = 10 //1024
-  val MemPredPCWidth = log2Up(WaitTableSize)
-  
-  // wait table parameters
-  val WaitTableSize = 1024
-
-  // store set parameters
-  val SSITSize = WaitTableSize
-  val LFSTSize = 32
-  val SSIDWidth = log2Up(LFSTSize)
-}

src/main/scala/xiangshan/backend/decode/StoreSet.scala

@@ -4,19 +4,21 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import utils._
+import xiangshan.mem.{LqPtr, SqPtr}
+import xiangshan.backend.roq.RoqPtr
 
 // store set load violation predictor
 // See "Memory Dependence Prediction using Store Sets" for details
 
 // Store Set Identifier Table Entry
-class SSITEntry extends XSBundle with MemPredParameters {
+class SSITEntry extends XSBundle {
   val valid = Bool()
   val isload = Bool()
   val ssid = UInt(SSIDWidth.W) // store set identifier
 }
 
 // Store Set Identifier Table
-class SSIT extends XSModule with MemPredParameters {
+class SSIT extends XSModule {
   val io = IO(new Bundle {
     val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // xor hashed decode pc(VaddrBits-1, 1)
     val rdata = Vec(DecodeWidth, Output(new SSITEntry))
@@ -32,7 +34,7 @@ class SSIT extends XSModule with MemPredParameters {
   val resetCounter = RegInit(0.U(ResetTimeMax2Pow.W))
   resetCounter := resetCounter + 1.U
 
-  // read SSIT in rename stage
+  // read SSIT in decode stage
   for (i <- 0 until DecodeWidth) {
     // io.rdata(i) := (data(io.raddr(i))(1) || io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
     io.rdata(i).valid := valid(io.raddr(i))
@@ -122,7 +124,67 @@ class SSIT extends XSModule with MemPredParameters {
 }
 
 
-// class StoreSet extends XSModule with MemPredParameters {
-//   val io = IO(new Bundle {
-//   })
-// }
+// Last Fetched Store Table Entry
+class LFSTEntry extends XSBundle  {
+  val valid = Bool()
+  val sqIdx = new SqPtr
+  val roqIdx = new RoqPtr
+}
+
+class DispatchToLFST extends XSBundle  {
+  val sqIdx = new SqPtr
+  val roqIdx = new RoqPtr
+  val ssid = UInt(SSIDWidth.W)
+}
+
+// Last Fetched Store Table
+class LFST extends XSModule  {
+  val io = IO(new Bundle {
+    val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // xor hashed decode pc(VaddrBits-1, 1)
+    val ren = Vec(DecodeWidth, Input(Bool())) // ren iff uop.cf.storeSetHit
+    val rdata = Vec(DecodeWidth, Output(Bool()))
+    // val update = Input(new MemPredUpdateReq) // RegNext should be added outside
+    // when redirect, mark canceled store as invalid
+    val redirect = Input(Valid(new Redirect))
+    val flush = Input(Bool())
+    // when store is dispatched, mark it as valid
+    val dispatch = Vec(RenameWidth, Flipped(Valid(new DispatchToLFST)))
+    // when store issued, mark store as invalid
+    val storeIssue = Vec(exuParameters.StuCnt, Flipped(Valid(new ExuInput)))
+    val csrCtrl = Input(new CustomCSRCtrlIO)
+  })
+
+  // TODO: use MemTemplate
+  val valid = RegInit(VecInit(Seq.fill(LFSTSize)(false.B)))
+  val sqIdx = Reg(Vec(LFSTSize, new SqPtr))
+  val roqIdx = Reg(Vec(LFSTSize, new RoqPtr))
+
+  // read LFST in rename stage
+  for (i <- 0 until DecodeWidth) {
+    io.rdata(i) := (valid(io.raddr(i)) && io.ren(i) || io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
+  }
+
+  // when store is dispatched, mark it as valid
+  (0 until RenameWidth).map(i => {
+    when(io.dispatch(i).valid){
+      val waddr = io.dispatch(i).bits.ssid
+      valid(waddr) := true.B
+      sqIdx(waddr) := io.dispatch(i).bits.sqIdx
+      roqIdx(waddr) := io.dispatch(i).bits.roqIdx
+    }
+  })
+
+  // when store is issued, mark it as invalid
+  (0 until exuParameters.StuCnt).map(i => {
+    when(io.storeIssue(i).valid){
+      valid(io.storeIssue(i).bits.uop.ssid) := false.B
+    }
+  })
+
+  // when redirect, cancel store influenced
+  (0 until LFSTSize).map(i => {
+    when(roqIdx(i).needFlush(io.redirect, io.flush)){
+      valid(i) := false.B
+    }
+  })
+}
\ No newline at end of file

src/main/scala/xiangshan/backend/decode/WaitTable.scala

@@ -6,7 +6,7 @@ import xiangshan._
 import utils._
 
 // 21264-like wait table
-class WaitTable extends XSModule with MemPredParameters {
+class WaitTable extends XSModule {
   val io = IO(new Bundle {
     val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // decode pc(VaddrBits-1, 1)
     val rdata = Vec(DecodeWidth, Output(Bool())) // loadWaitBit

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -9,6 +9,7 @@ import xiangshan.backend.roq.{RoqPtr, RoqEnqIO}
 import xiangshan.backend.rename.RenameBypassInfo
 import xiangshan.mem.LsqEnqIO
 import xiangshan.backend.fu.HasExceptionNO
+import xiangshan.backend.decode.DispatchToLFST
 
 
 class PreDispatchInfo extends XSBundle {
@@ -44,6 +45,8 @@ class Dispatch1 extends XSModule with HasExceptionNO {
       val needAlloc = Vec(RenameWidth, Output(Bool()))
       val req = Vec(RenameWidth, ValidIO(new MicroOp))
     }
+    // to store set LFST
+    val lfst = Vec(RenameWidth, Valid(new DispatchToLFST))
   })
 
 
@@ -124,6 +127,13 @@ class Dispatch1 extends XSModule with HasExceptionNO {
 //    XSError(io.fromRename(i).valid && updatedUop(i).roqIdx.asUInt =/= io.enqRoq.resp(i).asUInt, "they should equal")
     updatedUop(i).lqIdx  := io.enqLsq.resp(i).lqIdx
     updatedUop(i).sqIdx  := io.enqLsq.resp(i).sqIdx
+
+    // update store set LFST
+    io.lfst(i).valid := io.fromRename(i).valid && updatedUop(i).cf.storeSetHit && isStore(i)
+    // or io.fromRename(i).ready && updatedUop(i).cf.storeSetHit && isStore(i), which is much slower
+    io.lfst(i).bits.roqIdx := updatedUop(i).roqIdx
+    io.lfst(i).bits.sqIdx := updatedUop(i).sqIdx
+    io.lfst(i).bits.ssid := updatedUop(i).ssid
   }
 
 

src/main/scala/xiangshan/frontend/IFU.scala

@@ -10,7 +10,6 @@ import chisel3.experimental.chiselName
 import freechips.rocketchip.tile.HasLazyRoCC
 import chisel3.ExcitingUtils._
 import xiangshan.backend.ftq.FtqPtr
-import xiangshan.backend.decode.MemPredParameters
 
 trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{
   def mmioBusWidth = 64
@@ -98,7 +97,7 @@ class PrevHalfInstr extends XSBundle {
 }
 
 @chiselName
-class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper with MemPredParameters
+class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper 
 {
   val io = IO(new IFUIO)
   val bpu = BPU(EnableBPU)

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -7,7 +7,6 @@ import xiangshan._
 import utils._
 import xiangshan.backend.fu.HasExceptionNO
 import xiangshan.backend.ftq.FtqPtr
-import xiangshan.backend.decode.MemPredParameters
 
 class IbufPtr extends CircularQueuePtr(IbufPtr.IBufSize) { }
 
@@ -29,7 +28,7 @@ class IBufferIO extends XSBundle {
 class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
   val io = IO(new IBufferIO)
 
-  class IBufEntry extends XSBundle with MemPredParameters {
+  class IBufEntry extends XSBundle {
     val inst = UInt(32.W)
     val pc = UInt(VAddrBits.W)
     val foldpc = UInt(MemPredPCWidth.W)