From 26549752984768835947f907d9c94ff0275da5e3 Mon Sep 17 00:00:00 2001 From: Lingrui98 Date: Wed, 17 Feb 2021 19:19:12 +0800 Subject: [PATCH] sram template: support multi-way write --- src/main/scala/utils/SRAMTemplate.scala | 18 +++++++++++++----- src/main/scala/xiangshan/backend/ftq/Ftq.scala | 2 +- src/main/scala/xiangshan/cache/ICache.scala | 2 +- .../cache/prefetch/BestOffsetPrefetch.scala | 4 ++-- src/main/scala/xiangshan/frontend/Bim.scala | 2 +- src/main/scala/xiangshan/frontend/Btb.scala | 6 +++--- src/main/scala/xiangshan/frontend/SC.scala | 2 +- src/main/scala/xiangshan/frontend/Tage.scala | 2 +- 8 files changed, 23 insertions(+), 15 deletions(-) diff --git a/src/main/scala/utils/SRAMTemplate.scala b/src/main/scala/utils/SRAMTemplate.scala index dee1697fd..88d1a6780 100644 --- a/src/main/scala/utils/SRAMTemplate.scala +++ b/src/main/scala/utils/SRAMTemplate.scala @@ -29,15 +29,20 @@ class SRAMBundleA(val set: Int) extends Bundle { } class SRAMBundleAW[T <: Data](private val gen: T, set: Int, val way: Int = 1) extends SRAMBundleA(set) { - val data = Output(gen) + val data = Output(Vec(way, gen)) val waymask = if (way > 1) Some(Output(UInt(way.W))) else None - def apply(data: T, setIdx: UInt, waymask: UInt) = { + def apply(data: Vec[T], setIdx: UInt, waymask: UInt): SRAMBundleAW[T] = { super.apply(setIdx) this.data := data this.waymask.map(_ := waymask) this } + // this could only be used when waymask is onehot or nway is 1 + def apply(data: T, setIdx: UInt, waymask: UInt): SRAMBundleAW[T] = { + apply(VecInit(Seq.fill(way)(data)), setIdx, waymask) + this + } } class SRAMBundleR[T <: Data](private val gen: T, val way: Int = 1) extends Bundle { @@ -58,11 +63,15 @@ class SRAMReadBus[T <: Data](private val gen: T, val set: Int, val way: Int = 1) class SRAMWriteBus[T <: Data](private val gen: T, val set: Int, val way: Int = 1) extends Bundle { val req = Decoupled(new SRAMBundleAW(gen, set, way)) - def apply(valid: Bool, data: T, setIdx: UInt, waymask: UInt) = { + def apply(valid: Bool, data: Vec[T], setIdx: UInt, waymask: UInt): SRAMWriteBus[T] = { this.req.bits.apply(data = data, setIdx = setIdx, waymask = waymask) this.req.valid := valid this } + def apply(valid: Bool, data: T, setIdx: UInt, waymask: UInt): SRAMWriteBus[T] = { + apply(valid, VecInit(Seq.fill(way)(data)), setIdx, waymask) + this + } } class SRAMTemplate[T <: Data](gen: T, set: Int, way: Int = 1, @@ -89,9 +98,8 @@ class SRAMTemplate[T <: Data](gen: T, set: Int, way: Int = 1, val realRen = (if (singlePort) ren && !wen else ren) val setIdx = Mux(resetState, resetSet, io.w.req.bits.setIdx) - val wdataword = Mux(resetState, 0.U.asTypeOf(wordType), io.w.req.bits.data.asUInt) + val wdata = VecInit(Mux(resetState, 0.U.asTypeOf(Vec(way, gen)), io.w.req.bits.data).map(_.asTypeOf(wordType))) val waymask = Mux(resetState, Fill(way, "b1".U), io.w.req.bits.waymask.getOrElse("b1".U)) - val wdata = VecInit(Seq.fill(way)(wdataword)) when (wen) { array.write(setIdx, wdata, waymask.asBools) } val rdata = (if (holdRead) ReadAndHold(array, io.r.req.bits.setIdx, realRen) diff --git a/src/main/scala/xiangshan/backend/ftq/Ftq.scala b/src/main/scala/xiangshan/backend/ftq/Ftq.scala index 03e3efcc0..9b7f5e636 100644 --- a/src/main/scala/xiangshan/backend/ftq/Ftq.scala +++ b/src/main/scala/xiangshan/backend/ftq/Ftq.scala @@ -53,7 +53,7 @@ class FtqNRSRAM[T <: Data](gen: T, numRead: Int) extends XSModule { io.rdata(i) := sram.io.r.resp.data(0) sram.io.w.req.valid := io.wen sram.io.w.req.bits.setIdx := io.waddr - sram.io.w.req.bits.data := io.wdata + sram.io.w.req.bits.data := VecInit(io.wdata) } } diff --git a/src/main/scala/xiangshan/cache/ICache.scala b/src/main/scala/xiangshan/cache/ICache.scala index 336c35e87..6a1392908 100644 --- a/src/main/scala/xiangshan/cache/ICache.scala +++ b/src/main/scala/xiangshan/cache/ICache.scala @@ -261,7 +261,7 @@ class ICacheDataArray extends ICachArray for(b <- 0 until nBanks){ dataArray(w)(b).io.w.req.valid := io.write.valid && w.U === write_way dataArray(w)(b).io.w.req.bits.setIdx := write.virIdx - dataArray(w)(b).io.w.req.bits.data := write_bank_data(b) + dataArray(w)(b).io.w.req.bits.data := VecInit(write_bank_data(b)) } } diff --git a/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala b/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala index e4d5b0ed2..197bb894e 100644 --- a/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala +++ b/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala @@ -158,8 +158,8 @@ class RecentRequestTable(p: BOPParameters) extends PrefetchModule { val wAddr = io.w.bits rrTable.io.w.req.valid := io.w.valid && !io.r.req.valid rrTable.io.w.req.bits.setIdx := idx(wAddr) - rrTable.io.w.req.bits.data.valid := true.B - rrTable.io.w.req.bits.data.tag := tag(wAddr) + rrTable.io.w.req.bits.data(0).valid := true.B + rrTable.io.w.req.bits.data(0).tag := tag(wAddr) val rAddr = io.r.req.bits.addr - (io.r.req.bits.testOffset << log2Up(blockBytes)) val rData = Wire(rrTableEntry()) diff --git a/src/main/scala/xiangshan/frontend/Bim.scala b/src/main/scala/xiangshan/frontend/Bim.scala index 1faad23bf..1d958b11d 100644 --- a/src/main/scala/xiangshan/frontend/Bim.scala +++ b/src/main/scala/xiangshan/frontend/Bim.scala @@ -105,7 +105,7 @@ class BIM extends BasePredictor with BimParams { for (b <- 0 until BimBanks) { bim(b).io.w.req.valid := needToUpdate(b) || doing_reset bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow) - bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), newCtrs(b)) + bim(b).io.w.req.bits.data := VecInit(Mux(doing_reset, 2.U(2.W), newCtrs(b))) } if (BPUDebug && debug) { diff --git a/src/main/scala/xiangshan/frontend/Btb.scala b/src/main/scala/xiangshan/frontend/Btb.scala index b2ebf4631..7ec7ecb53 100644 --- a/src/main/scala/xiangshan/frontend/Btb.scala +++ b/src/main/scala/xiangshan/frontend/Btb.scala @@ -198,16 +198,16 @@ class BTB extends BasePredictor with BTBParams{ for (b <- 0 until BtbBanks) { meta(w)(b).io.w.req.valid := updateValid && b.U === updateBank && w.U === updateWay meta(w)(b).io.w.req.bits.setIdx := updateRow - meta(w)(b).io.w.req.bits.data := metaWrite + meta(w)(b).io.w.req.bits.data := VecInit(metaWrite) data(w)(b).io.w.req.valid := updateValid && b.U === updateBank && w.U === updateWay data(w)(b).io.w.req.bits.setIdx := updateRow - data(w)(b).io.w.req.bits.data := dataWrite + data(w)(b).io.w.req.bits.data := VecInit(dataWrite) } } edata.io.w.req.valid := updateValid && new_extended edata.io.w.req.bits.setIdx := updateRow - edata.io.w.req.bits.data := u.target + edata.io.w.req.bits.data := VecInit(u.target) if (BPUDebug && debug) { diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala index 1f4c396c9..9526ab9f7 100644 --- a/src/main/scala/xiangshan/frontend/SC.scala +++ b/src/main/scala/xiangshan/frontend/SC.scala @@ -96,7 +96,7 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int) extends BaseSC table(b)(i).io.w.req.valid := (io.update.mask(b) && i.U === io.update.tagePred.asUInt) || doing_reset table(b)(i).io.w.req.bits.setIdx := Mux(doing_reset, reset_idx, update_idx) - table(b)(i).io.w.req.bits.data := Mux(doing_reset, 0.S, update_wdata) + table(b)(i).io.w.req.bits.data := VecInit(Mux(doing_reset, 0.S, update_wdata)) } } diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala index ed67c3106..ce498210b 100644 --- a/src/main/scala/xiangshan/frontend/Tage.scala +++ b/src/main/scala/xiangshan/frontend/Tage.scala @@ -218,7 +218,7 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio (0 until TageBanks).map(b => { table(b).io.w.req.valid := io.update.mask(b) || doing_reset table(b).io.w.req.bits.setIdx := Mux(doing_reset, reset_idx, update_idx) - table(b).io.w.req.bits.data := Mux(doing_reset, 0.U.asTypeOf(new TageEntry), update_wdata(b)) + table(b).io.w.req.bits.data := VecInit(Mux(doing_reset, 0.U.asTypeOf(new TageEntry), update_wdata(b))) }) val update_hi_wdata = Wire(Vec(TageBanks, Bool())) -- GitLab