Merge pull request #434 from RISCVERS/fix-rvc-bug

Fix RVC bug: get imm from expanded instructions

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -36,7 +36,7 @@ class DecodeStage extends XSModule {
     val thisBrqValid = !io.in(i).bits.brUpdate.pd.notCFI || isMret || isSret
     io.enqBrq.needAlloc(i) := thisBrqValid
     io.enqBrq.req(i).valid := io.in(i).valid && thisBrqValid && io.out(i).ready
-    io.enqBrq.req(i).bits  := io.in(i).bits
+    io.enqBrq.req(i).bits  := decoders(i).io.deq.cf_ctrl.cf
 
     io.out(i).valid      := io.in(i).valid && io.enqBrq.req(i).ready
     io.out(i).bits       := decoders(i).io.deq.cf_ctrl

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -447,7 +447,7 @@ class DecodeUnit extends XSModule with DecodeUnitConstants {
   val cs = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table)
 
   val fpDecoder = Module(new FPDecoder)
-  fpDecoder.io.instr := io.enq.ctrl_flow.instr
+  fpDecoder.io.instr := ctrl_flow.instr
   cs.fpu := fpDecoder.io.fpCtrl
 
   // read src1~3 location
@@ -475,10 +475,9 @@ class DecodeUnit extends XSModule with DecodeUnitConstants {
     cs.lsrc1 := XSTrapDecode.lsrc1
   }
 
-  val instr = io.enq.ctrl_flow.instr
   cs.imm := LookupTree(cs.selImm, ImmUnion.immSelMap.map(
     x => {
-      val minBits = x._2.minBitsFromInstr(instr)
+      val minBits = x._2.minBitsFromInstr(ctrl_flow.instr)
       require(minBits.getWidth == x._2.len)
       x._1 -> minBits
     }