diff --git a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
index aa0f04bd40d9ba82cf803debb0669030baf1eb12..2fdbf5367bf0fe8e30b7fa3834dccdd93017be1a 100644
--- a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
@@ -78,6 +78,7 @@ class StoreUnit_S1 extends XSModule {
   // writeback store inst to lsq
   io.lsq.valid := io.in.valid // TODO: && ! FP
   io.lsq.bits := io.in.bits
+  io.lsq.bits.paddr := s1_paddr
   io.lsq.bits.miss := false.B
   io.lsq.bits.mmio := AddressSpace.isMMIO(s1_paddr)