提交 106f2817 编写于 作者: L LinJiawei

update to chisel 3.4

上级 d8bfd164
[submodule "rocket-chip"]
path = rocket-chip
url = https://github.com/chipsalliance/rocket-chip.git
branch = 2bdb03dbca3f77ad4c378cc1b95ab4961bc1448a
branch = d6bd3c61993637c3f10544c59e861fae8af29f39
[submodule "block-inclusivecache-sifive"]
path = block-inclusivecache-sifive
url = https://github.com/RISCVERS/block-inclusivecache-sifive.git
......
......@@ -133,7 +133,7 @@ clean:
init:
git submodule update --init
# do not use a recursive init to pull some not used submodules
@# do not use a recursive init to pull some not used submodules
cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat
.PHONY: verilog emu clean help init $(REF_SO)
......@@ -5,7 +5,7 @@ import scalalib._
import coursier.maven.MavenRepository
object CustomZincWorkerModule extends ZincWorkerModule {
def repositories() = Seq(
def repositories() = super.repositories ++ Seq(
MavenRepository("https://maven.aliyun.com/repository/public"),
MavenRepository("https://maven.aliyun.com/repository/apache-snapshots")
)
......@@ -26,7 +26,7 @@ trait CommonModule extends ScalaModule {
}
val rocketChisel = Agg(
ivy"edu.berkeley.cs::chisel3:3.3.1"
ivy"edu.berkeley.cs::chisel3:3.4.0"
)
object `rocket-chip` extends SbtModule with CommonModule {
......@@ -68,7 +68,7 @@ object XiangShan extends CommonModule with SbtModule {
override def forkArgs = Seq("-Xmx10G")
override def ivyDeps = super.ivyDeps() ++ Agg(
ivy"edu.berkeley.cs::chisel3:3.3.2"
ivy"edu.berkeley.cs::chisel3:3.4.0-RC3"
)
override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`, `block-inclusivecache-sifive`)
......
Subproject commit 2bdb03dbca3f77ad4c378cc1b95ab4961bc1448a
Subproject commit d6bd3c61993637c3f10544c59e861fae8af29f39
......@@ -40,7 +40,7 @@ class ShowPrintTransform extends Transform with DependencyAPIMigration {
def findSubModules(m: DefModule): Unit = {
def viewStmt(s: Statement): Statement = s match {
case DefInstance(_, name, module) =>
case DefInstance(_, name, module, _) =>
ancestors(module) = ancestors(m.name) + m.name
queue += module
s
......
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