Merge pull request #210 from RISCVERS/debian-gogogo

MissQueue: for read hit, remember to set new_coh in decide_next_state

src/main/scala/xiangshan/cache/missQueue.scala

@@ -230,6 +230,7 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
         when (req.cmd === M_XRD) {
           // normal read
           // read hit, no need to update meta
+          new_coh   := old_coh
           new_state := s_send_resp
         } .otherwise {
           assert(isWrite(req.cmd))
@@ -301,7 +302,12 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
 
     when (edge.hasData(io.mem_grant.bits)) {
       when (io.mem_grant.fire()) {
-        assert(should_refill_data)
+        // for AcquireBlock BtoT, we clear should_refill_data
+        // and expect response with no data(Grant, not GrantData)
+        // but block inclusive cache responded with a GrantData!
+        // so we temporarily removed this assertion
+        // we may consider using AcquirePerm BtoT for permission upgrade
+        // assert(should_refill_data)
         refill_ctr := refill_ctr + 1.U
         for (i <- 0 until beatRows) {
           val row = io.mem_grant.bits.data(rowBits * (i + 1) - 1, rowBits * i)