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体验新版 GitCode,发现更多精彩内容 >>
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06c91a3d
编写于
10月 26, 2020
作者:
W
William Wang
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差异文件
[WIP] LoadUnit: provide meta for dcache
上级
dd1ffd4d
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
11 addition
and
4 deletion
+11
-4
src/main/scala/xiangshan/mem/Memend.scala
src/main/scala/xiangshan/mem/Memend.scala
+1
-1
src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
...ain/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
+8
-1
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
+2
-2
未找到文件。
src/main/scala/xiangshan/mem/Memend.scala
浏览文件 @
06c91a3d
...
...
@@ -145,7 +145,7 @@ class Memend extends XSModule {
lsroq
.
io
.
stout
<>
io
.
backend
.
stout
lsroq
.
io
.
commits
<>
io
.
backend
.
commits
lsroq
.
io
.
dp1Req
<>
io
.
backend
.
dp1Req
lsroq
.
io
.
lsIdxs
<>
io
.
backend
.
lsIdxs
lsroq
.
io
.
lsIdxs
<>
io
.
backend
.
lsIdxs
lsroq
.
io
.
brqRedirect
:=
io
.
backend
.
redirect
lsroq
.
io
.
roqDeqPtr
:=
io
.
backend
.
roqDeqPtr
io
.
backend
.
replayAll
<>
lsroq
.
io
.
rollback
...
...
src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
浏览文件 @
06c91a3d
...
...
@@ -160,6 +160,12 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
io
.
dcache
.
req
.
bits
.
mask
:=
DontCare
io
.
dcache
.
req
.
bits
.
meta
.
id
:=
DontCare
// TODO: // FIXME
io
.
dcache
.
req
.
bits
.
meta
.
vaddr
:=
DontCare
// data(missRefillSel).vaddr
io
.
dcache
.
req
.
bits
.
meta
.
paddr
:=
missRefillBlockAddr
io
.
dcache
.
req
.
bits
.
meta
.
uop
:=
uop
(
missRefillSel
)
io
.
dcache
.
req
.
bits
.
meta
.
mmio
:=
false
.
B
// data(missRefillSel).mmio
io
.
dcache
.
req
.
bits
.
meta
.
tlb_miss
:=
false
.
B
io
.
dcache
.
req
.
bits
.
meta
.
mask
:=
DontCare
io
.
dcache
.
req
.
bits
.
meta
.
replay
:=
false
.
B
io
.
dcache
.
resp
.
ready
:=
true
.
B
...
...
@@ -266,7 +272,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
io
.
ldout
(
i
).
valid
:=
loadWbSelVec
(
loadWbSel
(
i
))
when
(
io
.
ldout
(
i
).
fire
())
{
writebacked
(
loadWbSel
(
i
))
:=
true
.
B
XSInfo
(
io
.
loadIn
(
i
).
valid
,
"load miss write to cbd idx %d pc 0x%x paddr %x data %x mmio %x\n"
,
XSInfo
(
"load miss write to cbd roqidx %d lqidx %d pc 0x%x paddr %x data %x mmio %x\n"
,
io
.
ldout
(
i
).
bits
.
uop
.
roqIdx
,
io
.
ldout
(
i
).
bits
.
uop
.
lqIdx
,
io
.
ldout
(
i
).
bits
.
uop
.
cf
.
pc
,
data
(
loadWbSel
(
i
)).
paddr
,
...
...
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
浏览文件 @
06c91a3d
...
...
@@ -253,7 +253,7 @@ class LoadUnit extends XSModule {
p
"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n"
)
XSDebug
(
load_s1
.
io
.
out
.
valid
,
p
"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, tlb_miss ${io.dtlb.resp.bits.miss}, "
+
p
"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}"
)
p
"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}
\n
"
)
// writeback to LSROQ
// Current dcache use MSHR
...
...
@@ -279,7 +279,7 @@ class LoadUnit extends XSModule {
// io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut
load_s2
.
io
.
out
.
ready
:=
true
.
B
io
.
lsroq
.
ldout
.
ready
:=
!
hitLoadOut
.
valid
io
.
ldout
.
bits
:=
Mux
(
load_s2
.
io
.
out
.
ready
,
hitLoadOut
.
bits
,
io
.
lsroq
.
ldout
.
bits
)
io
.
ldout
.
bits
:=
Mux
(
hitLoadOut
.
valid
,
hitLoadOut
.
bits
,
io
.
lsroq
.
ldout
.
bits
)
io
.
ldout
.
valid
:=
hitLoadOut
.
valid
||
io
.
lsroq
.
ldout
.
valid
when
(
io
.
ldout
.
fire
()){
...
...
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