From 06c91a3d38dd208d04fdc57170a02ad9dfa0a957 Mon Sep 17 00:00:00 2001
From: William Wang <zeweiwang@outlook.com>
Date: Mon, 26 Oct 2020 17:31:38 +0800
Subject: [PATCH] [WIP] LoadUnit: provide meta for dcache

---
 src/main/scala/xiangshan/mem/Memend.scala                | 2 +-
 .../xiangshan/mem/lsqueue/separated/LoadQueue.scala      | 9 ++++++++-
 src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala     | 4 ++--
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/xiangshan/mem/Memend.scala b/src/main/scala/xiangshan/mem/Memend.scala
index 8aa03ddb7..e095b9315 100644
--- a/src/main/scala/xiangshan/mem/Memend.scala
+++ b/src/main/scala/xiangshan/mem/Memend.scala
@@ -145,7 +145,7 @@ class Memend extends XSModule {
   lsroq.io.stout       <> io.backend.stout
   lsroq.io.commits     <> io.backend.commits
   lsroq.io.dp1Req      <> io.backend.dp1Req
-  lsroq.io.lsIdxs   <> io.backend.lsIdxs
+  lsroq.io.lsIdxs      <> io.backend.lsIdxs
   lsroq.io.brqRedirect := io.backend.redirect
   lsroq.io.roqDeqPtr := io.backend.roqDeqPtr
   io.backend.replayAll <> lsroq.io.rollback
diff --git a/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
index 80f130a12..b1a7e2255 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
@@ -160,6 +160,12 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
   io.dcache.req.bits.mask := DontCare
 
   io.dcache.req.bits.meta.id       := DontCare // TODO: // FIXME
+  io.dcache.req.bits.meta.vaddr    := DontCare // data(missRefillSel).vaddr
+  io.dcache.req.bits.meta.paddr    := missRefillBlockAddr
+  io.dcache.req.bits.meta.uop      := uop(missRefillSel)
+  io.dcache.req.bits.meta.mmio     := false.B // data(missRefillSel).mmio
+  io.dcache.req.bits.meta.tlb_miss := false.B
+  io.dcache.req.bits.meta.mask     := DontCare
   io.dcache.req.bits.meta.replay   := false.B
 
   io.dcache.resp.ready := true.B
@@ -266,7 +272,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
     io.ldout(i).valid := loadWbSelVec(loadWbSel(i))
     when(io.ldout(i).fire()) {
       writebacked(loadWbSel(i)) := true.B
-      XSInfo(io.loadIn(i).valid, "load miss write to cbd idx %d pc 0x%x paddr %x data %x mmio %x\n",
+      XSInfo("load miss write to cbd roqidx %d lqidx %d pc 0x%x paddr %x data %x mmio %x\n",
+        io.ldout(i).bits.uop.roqIdx,
         io.ldout(i).bits.uop.lqIdx,
         io.ldout(i).bits.uop.cf.pc,
         data(loadWbSel(i)).paddr,
diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
index ab946f67a..1d2aae7a9 100644
--- a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
@@ -253,7 +253,7 @@ class LoadUnit extends XSModule {
     p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n")
   XSDebug(load_s1.io.out.valid, 
     p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 
-    p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}")
+    p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n")
 
   // writeback to LSROQ
   // Current dcache use MSHR
@@ -279,7 +279,7 @@ class LoadUnit extends XSModule {
   // io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut
   load_s2.io.out.ready := true.B
   io.lsroq.ldout.ready := !hitLoadOut.valid
-  io.ldout.bits := Mux(load_s2.io.out.ready, hitLoadOut.bits, io.lsroq.ldout.bits)
+  io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsroq.ldout.bits)
   io.ldout.valid := hitLoadOut.valid || io.lsroq.ldout.valid
 
   when(io.ldout.fire()){
-- 
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