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提交
0162f462
编写于
4月 24, 2023
作者:
C
czw
提交者:
huxuan0307
6月 12, 2023
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
type(FpWb): delete FpWB & rename VecWB to VfWB
上级
745be3cf
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
10 addition
and
18 deletion
+10
-18
src/main/scala/xiangshan/Parameters.scala
src/main/scala/xiangshan/Parameters.scala
+2
-2
src/main/scala/xiangshan/backend/Backend.scala
src/main/scala/xiangshan/backend/Backend.scala
+1
-1
src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
...in/scala/xiangshan/backend/datapath/WbArbiterParams.scala
+3
-3
src/main/scala/xiangshan/backend/datapath/WbConfig.scala
src/main/scala/xiangshan/backend/datapath/WbConfig.scala
+1
-9
src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
+3
-3
未找到文件。
src/main/scala/xiangshan/Parameters.scala
浏览文件 @
0162f462
...
@@ -356,8 +356,8 @@ case class XSCoreParameters
...
@@ -356,8 +356,8 @@ case class XSCoreParameters
SchdBlockParams
(
Seq
(
SchdBlockParams
(
Seq
(
IssueBlockParams
(
Seq
(
IssueBlockParams
(
Seq
(
ExeUnitParams
(
Seq
(
LduCfg
),
Seq
(
IntWB
(
5
,
0
),
V
ec
WB
(
4
,
0
)),
Seq
(
Seq
(
IntRD
(
8
,
0
)))),
ExeUnitParams
(
Seq
(
LduCfg
),
Seq
(
IntWB
(
5
,
0
),
V
f
WB
(
4
,
0
)),
Seq
(
Seq
(
IntRD
(
8
,
0
)))),
ExeUnitParams
(
Seq
(
LduCfg
),
Seq
(
IntWB
(
6
,
0
),
V
ec
WB
(
5
,
0
)),
Seq
(
Seq
(
IntRD
(
9
,
0
)))),
ExeUnitParams
(
Seq
(
LduCfg
),
Seq
(
IntWB
(
6
,
0
),
V
f
WB
(
5
,
0
)),
Seq
(
Seq
(
IntRD
(
9
,
0
)))),
),
numEntries
=
8
,
pregBits
=
pregBits
,
numWakeupFromWB
=
16
,
numEnq
=
2
),
),
numEntries
=
8
,
pregBits
=
pregBits
,
numWakeupFromWB
=
16
,
numEnq
=
2
),
IssueBlockParams
(
Seq
(
IssueBlockParams
(
Seq
(
ExeUnitParams
(
Seq
(
StaCfg
,
MouCfg
),
Seq
(
IntWB
(
5
,
1
)),
Seq
(
Seq
(
IntRD
(
10
,
0
)))),
ExeUnitParams
(
Seq
(
StaCfg
,
MouCfg
),
Seq
(
IntWB
(
5
,
1
)),
Seq
(
Seq
(
IntRD
(
10
,
0
)))),
...
...
src/main/scala/xiangshan/backend/Backend.scala
浏览文件 @
0162f462
...
@@ -29,7 +29,7 @@ class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyMod
...
@@ -29,7 +29,7 @@ class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyMod
require
(
wbPortConfigs
.
collectFirst
{
case
x
:
IntWB
=>
x
}.
nonEmpty
==
require
(
wbPortConfigs
.
collectFirst
{
case
x
:
IntWB
=>
x
}.
nonEmpty
==
fuConfigs
.
map
(
_
.
writeIntRf
).
reduce
(
_
||
_
),
fuConfigs
.
map
(
_
.
writeIntRf
).
reduce
(
_
||
_
),
"int wb port has no priority"
)
"int wb port has no priority"
)
require
(
wbPortConfigs
.
collectFirst
{
case
x
:
V
ec
WB
=>
x
}.
nonEmpty
==
require
(
wbPortConfigs
.
collectFirst
{
case
x
:
V
f
WB
=>
x
}.
nonEmpty
==
fuConfigs
.
map
(
x
=>
x
.
writeFpRf
||
x
.
writeVecRf
).
reduce
(
_
||
_
),
fuConfigs
.
map
(
x
=>
x
.
writeFpRf
||
x
.
writeVecRf
).
reduce
(
_
||
_
),
"vec wb port has no priority"
)
"vec wb port has no priority"
)
}
}
...
...
src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
浏览文件 @
0162f462
...
@@ -5,7 +5,7 @@ import chisel3.Output
...
@@ -5,7 +5,7 @@ import chisel3.Output
import
chisel3.util.
{
DecoupledIO
,
MixedVec
,
ValidIO
,
log2Up
}
import
chisel3.util.
{
DecoupledIO
,
MixedVec
,
ValidIO
,
log2Up
}
import
xiangshan.backend.Bundles.WriteBackBundle
import
xiangshan.backend.Bundles.WriteBackBundle
import
xiangshan.backend.datapath.DataConfig.
{
FpData
,
IntData
,
VecData
}
import
xiangshan.backend.datapath.DataConfig.
{
FpData
,
IntData
,
VecData
}
import
xiangshan.backend.datapath.WbConfig.
{
FpWB
,
IntWB
,
Vec
WB
,
WbConfig
}
import
xiangshan.backend.datapath.WbConfig.
{
IntWB
,
Vf
WB
,
WbConfig
}
import
xiangshan.backend.regfile.PregParams
import
xiangshan.backend.regfile.PregParams
case
class
WbArbiterParams
(
case
class
WbArbiterParams
(
...
@@ -31,8 +31,8 @@ case class WbArbiterParams(
...
@@ -31,8 +31,8 @@ case class WbArbiterParams(
ValidIO
(
new
WriteBackBundle
(
ValidIO
(
new
WriteBackBundle
(
wbCfgs
.
head
.
dataCfg
match
{
wbCfgs
.
head
.
dataCfg
match
{
case
IntData
()
=>
IntWB
(
port
=
x
)
case
IntData
()
=>
IntWB
(
port
=
x
)
case
FpData
()
=>
Fp
WB
(
port
=
x
)
case
FpData
()
=>
Vf
WB
(
port
=
x
)
case
VecData
()
=>
V
ec
WB
(
port
=
x
)
case
VecData
()
=>
V
f
WB
(
port
=
x
)
case
_
=>
???
case
_
=>
???
}
}
)
)
...
...
src/main/scala/xiangshan/backend/datapath/WbConfig.scala
浏览文件 @
0162f462
...
@@ -31,15 +31,7 @@ object WbConfig {
...
@@ -31,15 +31,7 @@ object WbConfig {
override
def
numPreg
:
Int
=
160
override
def
numPreg
:
Int
=
160
}
}
case
class
FpWB
(
case
class
VfWB
(
port
:
Int
=
-
1
,
priority
:
Int
=
Int
.
MaxValue
,
)
extends
PregWB
{
def
dataCfg
:
DataConfig
=
FpData
()
override
def
numPreg
:
Int
=
160
}
case
class
VecWB
(
port
:
Int
=
-
1
,
port
:
Int
=
-
1
,
priority
:
Int
=
Int
.
MaxValue
,
priority
:
Int
=
Int
.
MaxValue
,
)
extends
PregWB
{
)
extends
PregWB
{
...
...
src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
浏览文件 @
0162f462
...
@@ -6,7 +6,7 @@ import chisel3.util._
...
@@ -6,7 +6,7 @@ import chisel3.util._
import
xiangshan.backend.Bundles.
{
ExuInput
,
ExuOutput
}
import
xiangshan.backend.Bundles.
{
ExuInput
,
ExuOutput
}
import
xiangshan.backend.datapath.DataConfig.DataConfig
import
xiangshan.backend.datapath.DataConfig.DataConfig
import
xiangshan.backend.datapath.RdConfig._
import
xiangshan.backend.datapath.RdConfig._
import
xiangshan.backend.datapath.WbConfig.
{
Fp
WB
,
IntWB
,
WbConfig
}
import
xiangshan.backend.datapath.WbConfig.
{
Vf
WB
,
IntWB
,
WbConfig
}
import
xiangshan.backend.fu.
{
FuConfig
,
FuType
}
import
xiangshan.backend.fu.
{
FuConfig
,
FuType
}
import
xiangshan.backend.issue.
{
IntScheduler
,
SchedulerType
,
VfScheduler
}
import
xiangshan.backend.issue.
{
IntScheduler
,
SchedulerType
,
VfScheduler
}
...
@@ -103,9 +103,9 @@ case class ExeUnitParams(
...
@@ -103,9 +103,9 @@ case class ExeUnitParams(
}
}
}
}
def
get
Fp
WBPort
=
{
def
get
Vf
WBPort
=
{
wbPortConfigs
.
collectFirst
{
wbPortConfigs
.
collectFirst
{
case
x
:
Fp
WB
=>
x
case
x
:
Vf
WB
=>
x
}
}
}
}
...
...
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