type(FpWb): delete FpWB & rename VecWB to VfWB

src/main/scala/xiangshan/Parameters.scala

@@ -356,8 +356,8 @@ case class XSCoreParameters
 
     SchdBlockParams(Seq(
       IssueBlockParams(Seq(
-        ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))),
-        ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))),
+        ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VfWB(4, 0)), Seq(Seq(IntRD(8, 0)))),
+        ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VfWB(5, 0)), Seq(Seq(IntRD(9, 0)))),
       ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))),

src/main/scala/xiangshan/backend/Backend.scala

@@ -29,7 +29,7 @@ class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyMod
     require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty ==
       fuConfigs.map(_.writeIntRf).reduce(_ || _),
       "int wb port has no priority" )
-    require(wbPortConfigs.collectFirst { case x: VecWB => x }.nonEmpty ==
+    require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty ==
       fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _),
       "vec wb port has no priority" )
   }

src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala

@@ -5,7 +5,7 @@ import chisel3.Output
 import chisel3.util.{DecoupledIO, MixedVec, ValidIO, log2Up}
 import xiangshan.backend.Bundles.WriteBackBundle
 import xiangshan.backend.datapath.DataConfig.{FpData, IntData, VecData}
-import xiangshan.backend.datapath.WbConfig.{FpWB, IntWB, VecWB, WbConfig}
+import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig}
 import xiangshan.backend.regfile.PregParams
 
 case class WbArbiterParams(
@@ -31,8 +31,8 @@ case class WbArbiterParams(
         ValidIO(new WriteBackBundle(
           wbCfgs.head.dataCfg match {
             case IntData() => IntWB(port = x)
-            case FpData() => FpWB(port = x)
-            case VecData() => VecWB(port = x)
+            case FpData() => VfWB(port = x)
+            case VecData() => VfWB(port = x)
             case _ => ???
           }
         )

src/main/scala/xiangshan/backend/datapath/WbConfig.scala

@@ -31,15 +31,7 @@ object WbConfig {
     override def numPreg: Int = 160
   }
 
-  case class FpWB(
-    port    : Int = -1,
-    priority: Int = Int.MaxValue,
-  ) extends PregWB {
-    def dataCfg: DataConfig = FpData()
-    override def numPreg: Int = 160
-  }
-
-  case class VecWB(
+  case class VfWB(
     port    : Int = -1,
     priority: Int = Int.MaxValue,
   ) extends PregWB {

src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala

@@ -6,7 +6,7 @@ import chisel3.util._
 import xiangshan.backend.Bundles.{ExuInput, ExuOutput}
 import xiangshan.backend.datapath.DataConfig.DataConfig
 import xiangshan.backend.datapath.RdConfig._
-import xiangshan.backend.datapath.WbConfig.{FpWB, IntWB, WbConfig}
+import xiangshan.backend.datapath.WbConfig.{VfWB, IntWB, WbConfig}
 import xiangshan.backend.fu.{FuConfig, FuType}
 import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler}
 
@@ -103,9 +103,9 @@ case class ExeUnitParams(
     }
   }
 
-  def getFpWBPort = {
+  def getVfWBPort = {
     wbPortConfigs.collectFirst {
-      case x: FpWB => x
+      case x: VfWB => x
     }
   }