backend: refactor

* Prepare for merge master

src/main/scala/xiangshan/Bundle.scala

@@ -22,7 +22,6 @@ import chisel3.util.BitPat.bitPatToUInt
 import chisel3.util._
 import utility._
 import utils._
-import xiangshan.backend.ctrlblock.CtrlToFtqIO
 import xiangshan.backend.decode.{ImmUnion, XDecode}
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.rob.RobPtr
@@ -45,6 +44,7 @@ import Chisel.experimental.chiselName
 import chipsalliance.rocketchip.config.Parameters
 import chisel3.util.BitPat.bitPatToUInt
 import chisel3.util.experimental.decode.EspressoMinimizer
+import xiangshan.backend.CtrlToFtqIO
 import xiangshan.backend.fu.PMPEntry
 import xiangshan.frontend.Ftq_Redirect_SRAMEntry
 import xiangshan.frontend.AllFoldedHistories

src/main/scala/xiangshan/backend/Backend.scala

@@ -7,7 +7,6 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility.ZeroExt
 import xiangshan._
 import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput}
-import xiangshan.backend.ctrlblock.CtrlBlock
 import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
 import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD}
 import xiangshan.backend.datapath.WbConfig._

src/main/scala/xiangshan/backend/ctrlblock/CtrlBlock.scala → src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -14,7 +14,7 @@
 * See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
-package xiangshan.backend.ctrlblock
+package xiangshan.backend
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
@@ -24,14 +24,13 @@ import utility._
 import utils._
 import xiangshan.ExceptionNO._
 import xiangshan._
-import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles.{DecodedInst, DynInst, ExceptionInfo, ExuOutput}
+import xiangshan.backend.ctrlblock.{MemCtrl, RedirectGenerator}
 import xiangshan.backend.datapath.DataConfig.VAddrData
 import xiangshan.backend.decode.{DecodeStage, FusionDecoder}
 import xiangshan.backend.dispatch.{Dispatch, DispatchQueue}
 import xiangshan.backend.fu.PFEvent
 import xiangshan.backend.fu.vector.Bundles.VType
-import xiangshan.backend.regfile.RfReadPort
 import xiangshan.backend.rename.{Rename, RenameTableWrapper}
 import xiangshan.backend.rob.{Rob, RobCSRIO, RobLsqIO}
 import xiangshan.frontend.{FtqRead, Ftq_RF_Components}

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -25,7 +25,7 @@ import xiangshan._
 import xiangshan.frontend.icache._
 import xiangshan.backend.decode.ImmUnion
 import utility.ChiselDB
-import xiangshan.backend.ctrlblock.CtrlToFtqIO
+import xiangshan.backend.CtrlToFtqIO
 
 class FtqDebugBundle extends Bundle {
   val pc = UInt(39.W)