* Replace Softsign Eigen with c implementation
test=develop

* Optimize softmax. When the input tensor is 2-D and axis is 1, there is no need to resize.

* Optimize the gru, avoid calling Tensor::Slice.
test=develop

* Remove a std::vector in softmax.
test=develop

* Define CalculateSeqWidth to get the width of a sequence.
test=develop

* comment All opencl buffer kernels. test=develop

* refactor conv, depthwise into one routing selection. test=develop

* [LITE][BM] support VGG,Inception,Mobilenet,Darknet, test=develop

* [LITE][OPENCL] Add opencl image2d conv3x3. test=develop

* [LITE][OPENCL]Add scale kernel.

* [LITE][OPENCL]Add scale kernel, format code style.

add concat ut, test=develop

* fix axis compute, test=develop

* add other axis, test=develop

* fix ut. test=develop

* [ARM] add 5x5s2 depthwise conv armv8 impl, test=develop

* [ARM] add int8 5x5s2 dw conv armv7 impl, test=develop

* [ARM] add int8 5x5s2 dw conv impl, test=develop

* [ARM] close int8 conv ut, test=develop

[OPENCL] add sigmoid image2d kernel and ut

* fix: update fpga backend and kernel
test=develop

* style: style fix
test=develop

* Optimize the transform from Paddle' Tensor to EigenVector, avoiding defining multiple DDim.

* Optimize the compute implementation of several operators.
test=develop

* Optimize the InferShape of several operators.
test=develop

* Remove the new function, resize and CheckPositive in DDim.
test=develop

* Fix a bug in fc_op's InferShape.
test=develop

[LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FusionElemenwiseAddAct op with opencl image format (#2844)

* [LITE][OPENCL] Add 3 kernels of ElementwiseAdd/FuseElementwiseAdd op. test=develop

* [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,test=develop

* [LITE][OPENCL][Image]develop 1x1/5x5/7x7 routing in conv_compute ,convert bias filter in prepare for run ,test=develop

* [LITE][OPENCL] remove useless code. test=develop

* [LITE][OPENCL] finish 4 kernel and unit tests of image2d opencl elementwise_mul kernel. test=develop

* [LITE][OPENCL] Fix little bug of ASSERT. test=develop

* [LITE][OPENCL] Fix bug of channel_mul_d2 and d4. test=develop

* refactor 5x5s1 dw conv armv8, test=develop

* [ARM] refactor depthwise conv 5x5s1, and support relu6, leakey relu, test=develop

* [ARM] sgemv support fuse relu6 and leakey relu,test=develop

* [ARM] reduce some conv ut case, test=develop

* [ARM] fix 5x5dw conv pick kernel bug, test=develop

* fix code style, test=develop

* [ARM] fix sgemv fuse relu6 bug, test=develop

* [ARM] fix fp32 5x5s1 dw bug, test=develop

* [ARM] fix fp32 5x5 dw conv pick kernel bug, test=develop

* [LITE][OPENCL]develop basic image depthwiseconv,passed loop test,test=develop

* [LITE][OPENCL]log to vlog(4),test=develop

* [LITE][OPENCL]fix depthwise buffer conv kernel name ,test=develop

- modify aligned_matmul kernel for dynamically malloc memory
- fix top_k_avg_pooling kernel to support data whose size is more than cuda shared memory.

* [NPU] reshape x,y,out node in elementwise ops

* [LITE][OPENCL] conv2d_1x1_image, choose simple kernel when in some case. for opencl ,test=develop

* [LITE][OPENCL] conv2d_1x1_image, add looptest ,test=develop

1. add conv_5x5s2_dw to support any padding
2. add 1x1s2pooling impl
3. fix conv dw 3x3 s1p01 bug

* fix, test=develop

* add fc_relu, test=develop

- 修复var_conv_2d级联使用中计算错误的bug
- x86的var_conv_2d中显示指定lod level为3

add gemm + relu6/leakyrelu fusion