merge fc commit

src/fpga/quantization.cpp

@@ -47,7 +47,7 @@ static Dtype find_max(Dtype* data, int64_t num) {
 }
 
 // template <typename Dtype>
-void quantize_filter(framework::Tensor *filter) {
+void quantize_filter(framework::Tensor* filter) {
   DLOG << "quantilize_filter........";
 
   float scale = 0;

src/fpga/quantization.h

@@ -24,7 +24,7 @@ template <typename Dtype>
 static void chw_to_hwc(Dtype* data_in, Dtype* data_out, int64_t num,
                        int64_t channel, int64_t height, int64_t width);
 
-void quantize_filter(framework::Tensor *filter);
+void quantize_filter(framework::Tensor* filter);
 
 }  // namespace fpga
 }  // namespace paddle_mobile

src/operators/kernel/fpga/conv_add_bn_kernel.cpp

@@ -60,7 +60,7 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam *param) {
   param->SetNewScale(new_scale);
   param->SetNewBias(new_bias);
 
-    fpga::quantize_filter(filter);
+  fpga::quantize_filter(filter);
   auto filter_ptr = filter->data<int8_t>();
 
   fpga::ConvArgs convArgs;

src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp

@@ -56,7 +56,7 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(FusionConvAddBNReluParam *param) {
   }
   param->SetNewScale(new_scale);
   param->SetNewBias(new_bias);
-    fpga::quantize_filter(filter);
+  fpga::quantize_filter(filter);
   auto filter_ptr = filter->data<int8_t>();
 
   fpga::ConvArgs convArgs;

src/operators/kernel/fpga/conv_add_relu_kernel.cpp

@@ -40,7 +40,7 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam *param) {
     bs_ptr[i * 2 + 1] = bias_ptr[i];
   }
 
-    fpga::quantize_filter(filter);
+  fpga::quantize_filter(filter);
   auto filter_ptr = filter->data<int8_t>();
 
   fpga::ConvArgs convArgs;

src/operators/kernel/fpga/conv_bn_kernel.cpp

@@ -55,7 +55,7 @@ bool ConvBNKernel<FPGA, float>::Init(FusionConvBNParam *param) {
   }
   param->SetNewScale(new_scale);
   param->SetNewBias(new_bias);
-    fpga::quantize_filter(filter);
+  fpga::quantize_filter(filter);
   auto filter_ptr = filter->data<int8_t>();
 
   fpga::ConvArgs convArgs;

src/operators/kernel/fpga/conv_bn_relu_kernel.cpp

@@ -52,7 +52,7 @@ bool ConvBNReluKernel<FPGA, float>::Init(FusionConvBNReluParam *param) {
   }
   param->SetNewScale(new_scale);
   param->SetNewBias(new_bias);
-    fpga::quantize_filter(filter);
+  fpga::quantize_filter(filter);
   auto filter_ptr = filter->data<int8_t>();
 
   fpga::ConvArgs convArgs;

src/operators/kernel/fpga/fc_relu_kernel.cpp

@@ -40,7 +40,7 @@ bool FusionFcReluKernel<FPGA, float>::Init(FusionFcReluParam *param) {
     bs_ptr[i * 2 + 1] = input_z_ptr[i];
   }
 
-    fpga::quantize_filter(input_y);
+  fpga::quantize_filter(input_y);
   auto input_y_ptr = input_y->data<int8_t>();
 
   fpga::ConvArgs convArgs;