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  1. 17 9月, 2016 6 次提交
  3. 27 6月, 2016 1 次提交
    • M
      common: Pass the boot device into spl_boot_mode() · 2b1cdafa
      由 Marek Vasut 提交于 
      The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.

The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NAndreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: NAndreas Bießmann <andreas@biessmann.org>
      2b1cdafa
  5. 08 6月, 2016 2 次提交
  7. 02 6月, 2016 1 次提交
    • M
      arm: socfpga: Add samtec VIN|ING board · 569a191a
      由 Marek Vasut 提交于 
      Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
 - 1 GiB of DRAM
 - 1 Gigabit ethernet
 - 1 USB gadget port
 - 1 USB host port with an on-board hub
 - 2 QSPI NORs connected to the Cadence QSPI core
 - Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request
      569a191a
  9. 07 5月, 2016 1 次提交
  11. 10 4月, 2016 2 次提交
    • M
      arm: socfpga: Nuke useless include · dafd5792
      由 Marek Vasut 提交于 
      The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
      dafd5792
    • M
      arm: socfpga: Handle phy-mode OF property for GMACs · 5f79d008
      由 Marek Vasut 提交于 
      Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.

This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.
Signed-off-by: NMarek Vasut <marex@denx.de>
Reported-by: NDenis Bakhvalov <denis.bakhvalov@nokia.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      5f79d008
  13. 25 2月, 2016 2 次提交
    • M
      arm: socfpga: Fix ethernet reset handling · e6e34ca3
      由 Marek Vasut 提交于 
      The following patch caused cpu_eth_init() to not be called anymore
for DM-capable boards:

commit c32a6fd0
Date:   Sun Jan 17 14:51:56 2016 -0700
    net: Don't call board/cpu_eth_init() with driver model

This breaks ethernet on SoCFPGA, since we use that function to un-reset
the ethernet blocks. Invoke the ethernet reset function from arch_misc_init()
instead to fix the breakage.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
      e6e34ca3
    • M
      arm: socfpga: Remove bashisms from qts filter · 80da8664
      由 Marek Vasut 提交于 
      Weed out bashisms from the script. The echo -e does not work in dash,
which is the default /bin/sh in debian .
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
      80da8664
  15. 16 1月, 2016 1 次提交
  17. 23 12月, 2015 3 次提交
  19. 22 12月, 2015 1 次提交
  21. 20 12月, 2015 4 次提交
  23. 07 12月, 2015 2 次提交
  25. 30 11月, 2015 4 次提交
  27. 04 11月, 2015 1 次提交
  29. 17 10月, 2015 1 次提交
    • D
      arm: socfpga: enable data/inst prefetch and shared override in the L2 · 8d8e13e1
      由 Dinh Nguyen 提交于 
      Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
      8d8e13e1
  31. 23 9月, 2015 1 次提交
  33. 04 9月, 2015 6 次提交
  35. 23 8月, 2015 1 次提交
    • M
      arm: socfpga: Make the pinmux table const u8 · cc9429a5
      由 Marek Vasut 提交于 
      Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.
Signed-off-by: NMarek Vasut <marex@denx.de>
      cc9429a5