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  1. 17 9月, 2016 18 次提交
  3. 07 9月, 2016 11 次提交
    • M
      ARM: am335x: select DM_GPIO · 174245b9
      由 Masahiro Yamada 提交于 
      We are supposed to not add config entries with only "default y"
in board/SoC Kconfig files.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
      174245b9
    • M
      ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig · 15446988
      由 Masahiro Yamada 提交于 
      Move this option to Kconfig and set its default value to 4; this
increases the number of supported CPUs for some boards.

It consumes 1KB memory per CPU for PSCI stack, but it should not
be a big deal, given the amount of memory used for the modern OSes.
Reviewed-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      15446988
    • M
      ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig · 217f92bb
      由 Masahiro Yamada 提交于 
      Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select.  Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      217f92bb
    • M
      ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI · 5a3aae68
      由 Masahiro Yamada 提交于 
      If CONFIG_ARMV7_NONSEC is enabled, the linker script requires
CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Reviewed-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      5a3aae68
    • M
      ARM: tegra: remove wrong dependency on SPL_BUILD · 55a65e61
      由 Masahiro Yamada 提交于 
      SPL_BUILD is not a CONFIG in Kconfig, so !SPL_BUILD is always true.
Reviewed-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      55a65e61
    • T
      TI: Rework SRAM definitions and maximums · fa2f81b0
      由 Tom Rini 提交于 
      On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area.  As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow.  As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.

Tested on OMAP4 Pandaboard, OMAP3 Beagle xM

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Weber <weber@corscience.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: "B, Ravi" <ravibabu@ti.com>
Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Tested-by: NLokesh Vutla <lokeshvutla@ti.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
Tested-by: NLadislav Michl <ladis@linux-mips.org>
      fa2f81b0
    • B
      meson: odroid-c2: enable Ethernet support through the device tree · cfe25561
      由 Beniamino Galvani 提交于 
      Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
      cfe25561
    • B
      arm: dts: update DTS files for meson-gxbb and odroid-c2 · dd83840e
      由 Beniamino Galvani 提交于 
      Import DTS files and dt-bindings includes from Linux 4.8-rc1.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
      dd83840e
    • A
      bcm2835_gpio: Implement GPIOF_FUNC · 04a993fe
      由 Alexander Graf 提交于 
      So far we could only tell the gpio framework that a GPIO was mapped as input or
output, not as alternative function.

This patch adds support for determining whether a function is mapped as
alternative.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
      04a993fe
    • F
      mx6: ddr: Allow changing REFSEL and REFR fields · edf00937
      由 Fabio Estevam 提交于 
      Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NEric Nelson <eric@nelint.com>
      edf00937
    • A
      arm: imx: Add support for Advantech DMS-BA16 board · ff383220
      由 Akshay Bhat 提交于 
      Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
      ff383220
  5. 06 9月, 2016 1 次提交
  7. 03 9月, 2016 5 次提交
  9. 02 9月, 2016 1 次提交
  11. 31 8月, 2016 1 次提交
    • S
      ARM: tegra: use numeric versioning for p2771-0000 · 7932d3e4
      由 Stephen Warren 提交于 
      The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric
versioning scheme, with version numbers such as 000/100/200/300/400/500.
Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00.
However, that numbering scheme is not easily visible outside of NVIDIA,
and so does not make much sense to use. Convert U-Boot to use the readily
visible numeric scheme.

Also, it turns out that the current A02 DT actually applies to board
versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200
so that all U-Boot builds are named after the first version of the HW they
support.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>
      7932d3e4
  13. 28 8月, 2016 3 次提交