Add some missing address translations from virtual address in local DRAM
to physical address, which is needed for the DMA transactions to work
correctly.

This issue was detected while testing the e1000 driver on the MIPS
Octeon III platform, which needs address translation.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>

Using (dm_)pci_virt_to_mem() is incorrect to translate the virtual
address in local DRAM to a physical address. The correct macro here
is virt_to_phys() so switch to using this macro.

As virt_to_bus() is now not used any more, this patch also removes
both definitions (DM and non-DM).

This issue was detected while testing the e1000 driver on the MIPS
Octeon III platform, which needs address translation.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>

bus_to_phys() is defined but not referenced at all. This patch removes
it completely.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>

So far all GBit users of the sun8i-emac driver were using the "rgmii"
PHY mode, even though this turns out to be wrong. It just worked because
the PHY driver doesn't do the proper setup (yet).
In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the
correct ones.

To allow the DTs to describe the phy-mode correctly, and to stay
compatible with Linux, at least allow those other RGMII modes in the
driver.

This avoids breakage if mainline DTs will be synced with U-Boot.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

This patch adds  ethernet driver for MediaTek MT7620 SoC.

The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in
7-port switch and two xMII interfaces (can be MII/RMII/RGMII).

The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be
configured to connect to either the intergrited FE PHY, or the xMII.
Port 5 always connects to the xMII. Port 6 is the CPU port.

This driver supports MT7530 giga switch connects to port 5.
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>

Take into account all RGMII interface types. Depending on it
the RGMII PHY's timings are setup.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Add support for SAMA7G5 EMAC.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Add support for SAMA7G5 GMAC.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

clk_set_rate() returns the set rate in case of success and a
negative number in case of failure. Consider failure only the
negative numbers.

Fixes: 3ef64444 ("dm: net: macb: Implement link speed change callback")
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Different implementation of USER IO register needs different
mapping for bit fields of this register. Add implementation
for this and, since clken is part of USER IO and it needs to
be activated based on per SoC capabilities, add caps in
macb_config where clken specific information needs to be filled.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NPatrice Chotard <patrice.chotard@foss.st.com>

A sporadic condition occurs when the "bad packet" error is triggered
repeatedly, which results in "bad packet" messages scrolling on the
console during transfer. To avoid triggering this, reset the internal
RXFC count on the first occurance of the "bad packet", which forces
the code to re-read the RX packet count from the MAC, and prevents
any additional "bad packet" messages if there are no more packets in
the MAC. Also print better debug information if this condition occurs.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Tom Rini <trini@konsulko.com>

Read and retain MAC address across flash and QEMU support.
Signed-off-by: NHongwei Zhang <hongweiz@ami.com>

Implement programming MAC address to the hardware also for device model
configuration.

Fixes: b565b18a ("board: ge: bx50v3: Enable DM for PCI and ethernet")
Signed-off-by: NIan Ray <ian.ray@ge.com>
Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.com>

Fix typo.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Add support for DLL setup on KSZ9131.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.

The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Add a return value to bb_miiphy_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: NOvidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: NSiew Chin Lim <elly.siew.chin.lim@intel.com>

At present ofnode is present in the device even if it is never used. With
of-platdata this field is not used, so can be removed. In preparation for
this, change the access to go through inline functions.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Most drivers use these access methods but a few do not. Update them.

In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NPratyush Yadav <p.yadav@ti.com>

Checking for seq == -1 is effectively checking that the device is
activated. The new sequence numbers are never -1 for a bound device, so
update the check.

Also drop the note about valid sequence numbers so it is accurate with the
new approach.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Several Octeon drivers operate by setting the sequence number of their
device. This should not be needed with the new sequence number setup. Also
it is not permitted. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present various drivers etc. access the device's 'seq' member directly.
This makes it harder to change the meaning of that member. Change access
to go through a function instead.

The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Rename this to be consistent with the change from 'platdata'.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This function is not needed since the standard device_bind() can be used
instead.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This function is not necessary anymore, since device_bind_ofnode() does
the same thing and works with both flattree and livetree.

Rename it to indicate that it is special.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
  Net:   SF: Detected s25fs512s with page size 256 Bytes, erase size 256
  KiB, total 64 MiB
  "Synchronous Abort" handler, esr 0x96000210
  elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
  elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
  x0 : 00000000b79407e8 x1 : 0000000040640000
  x2 : 0000000000000050 x3 : 0000000000000000
  x4 : 000000000000000a x5 : 0000000000000050
  x6 : 0000000000000366 x7 : 00000000b7942308
  x8 : 00000000b76407c0 x9 : 0000000000000008
  x10: 0000000000000044 x11: 00000000b7634d1c
  x12: 000000000000004f x13: 0000000000000044
  x14: 00000000b7634d98 x15: 00000000b76407c0
  x16: 0000000000000000 x17: 0000000000000000
  x18: 00000000b7636dd8 x19: 0000000000000000
  x20: 00000000b79407d0 x21: 00000000b79407e8
  x22: 0000000040640000 x23: 00000000b7634e58
  x24: 0000000000000000 x25: 0000000003800000
  x26: 00000000b7bdd000 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000b7634d10

  Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
  Resetting CPU ...
Signed-off-by: NBiwen Li <biwen.li@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.

LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.
Signed-off-by: NMeenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.
Signed-off-by: NMeenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

In case there is an EEPROM attached to the KS8851 MAC and the EEPROM
contains a valid MAC address, the MAC address is loaded into the NIC
registers on power on. Read the MAC address out of the NIC registers
and provide it to U-Boot.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>

As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.
Signed-off-by: NRazvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
[Rebased]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.
Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>

When sending a command via the MDIO bus, the Designware MAC expects some
bits in the CMD register to describe the clock divider value between
the main clock and the MDIO clock.
So far we were omitting these bits, resulting in setting "00", which
means "/ 16", so ending up with an MDIO frequency of either 18.75 or
12.5 MHz.
All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek
PHYs seem to be fine with that - although it looks like to be severly
overclocked (the MDIO spec limits the frequency to 2.5 MHz).
However the external 100Mbit PHY on the Pine64 (non-plus) board is
not happy with that, Ethernet was actually never working there, as the
PHY didn't probe.

As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit
SoCs), and use 200 MHz on the H3, we need the highest divider of 128
to let the MDIO clock end up below the required 2.5 MHz.

This enables Ethernet on the Pine64(non-plus).
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

The current implementation of sun8i_get_ephy_nodes() makes quite some
assumptions, in general relying on DT path names is a bad idea.
I think the idea of the code was to determine if we are using the
internal PHY, for which there are simpler and more robust methods:

Rewrite (and rename) the existing function to simply lookup the DT node
that "phy-handle" points to, using the device's DT node.
Then check whether the parent of that PHY node is using an "H3 internal
MDIO" compatible string. If we ever get another internal MDIO bus
implementation, we will probably need code adjustments anyway, so this
is good enough for now.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
[jagan: rebase on master]
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Acked-by: NMaxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>