- 27 1月, 2021 3 次提交
-
-
由 Stefan Roese 提交于
Add some missing address translations from virtual address in local DRAM to physical address, which is needed for the DMA transactions to work correctly. This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
-
由 Stefan Roese 提交于
Using (dm_)pci_virt_to_mem() is incorrect to translate the virtual address in local DRAM to a physical address. The correct macro here is virt_to_phys() so switch to using this macro. As virt_to_bus() is now not used any more, this patch also removes both definitions (DM and non-DM). This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
-
由 Stefan Roese 提交于
bus_to_phys() is defined but not referenced at all. This patch removes it completely. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
-
- 26 1月, 2021 8 次提交
-
-
由 Jernej Skrabec 提交于
This commit introduces DM H616 clock driver. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
-
由 Jernej Skrabec 提交于
H616 pinctrl is no different configuration wise than others, so just add compatible for it. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
-
由 Jernej Skrabec 提交于
H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
-
由 Andre Przywara 提交于
So far the only difference between the various Allwinner MMC controller we are concerned about is the mod clock register offset. This is actually not directly related to the MMC controller IP, but an integration choice, dependent on the SoC this appears in. To avoid becoming trapped with some compatible fallback strings, let's remove the whole struct sunxi_mmc_variant, and replace this with a SoC based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols. This will later simplify H616 support. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
-
由 Jernej Skrabec 提交于
While currently none of the newer Allwinner SoCs currently has I2C support implemented in U-Boot, this will change soon. mvtwsi driver is good as it is for them except one macro. Update it to be ready once I2C support lands for those SoCs. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NSamuel Holland <samuel@sholland.org> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
-
由 Jernej Skrabec 提交于
It turns out that several SoCs share same mmc configuration as H6. In order to lower ifdef clutter replace H6 specific macro with common one. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
-
由 Jernej Skrabec 提交于
This PMIC can be found on H616 boards and it's very similar to AXP805 and AXP806. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
-
由 Andre Przywara 提交于
So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
-
- 25 1月, 2021 12 次提交
-
-
由 Weijie Gao 提交于
Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can be probed before relocation even if u-boot,dm-pre-reloc is not present in the dts. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
Currently this driver does not set the value of plat->cfg.f_max, which results in that MMC framework will always run at the lowest frequency. This patch sets plat->cfg.f_max to the maximum allowed frequency, which equals to the source clock frequency. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
The driver is missing pad control settings (pad delay and pad conf) for the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will encounter CRC error on data transfers. This patch adds default pad control settings for mt7620_compat. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
It turns out that the sclk cycles used by mt7620/mt7628 is the same as other chips (20 bits, 1048576), not 65536. This patch removes sclk_cycle_shift from dev_comp, and uses a macro with a value 20 instead. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds ethernet driver for MediaTek MT7620 SoC. The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in 7-port switch and two xMII interfaces (can be MII/RMII/RGMII). The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be configured to connect to either the intergrited FE PHY, or the xMII. Port 5 always connects to the xMII. Port 6 is the CPU port. This driver supports MT7530 giga switch connects to port 5. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds USB PHY driver for MediaTek MT7620 SoC Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds spi controller support for MediaTek MT7620 SoC. The SPI controller supports two chip selects. These two chip selects are implemented as two separate register groups, but they share the same bus (DI/DO/CLK), only CS pins are dedicated for each register group. Appearently these two register groups cannot operates simulataneously so they are implemented as one controller. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds GPIO controller driver for MediaTek MT7620 SoC Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds watchdog support for the Mediatek MT7620 SoC Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds pinctrl support for MediaTek MT7620 SoC. The MT7620 SoC supports only pinmux. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
由 Weijie Gao 提交于
This patch adds uart support for MediaTek MT7620 and earlier SoCs. The UART used by MT7620 is incompatible with the ns16550a driver. All registers of this UART have different addresses. A special 16-bit register for Divisor Latch is used to set the baudrate instead of the original two 8-bit registers (DLL and DLM). The driver supports of-platdata which is useful for tiny SPL. Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
-
- 23 1月, 2021 8 次提交
-
-
由 Marek Vasut 提交于
In case the clock framework is enabled, enable the SPI controller clock and obtain max frequency from the clock framework. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
-
由 Marek Vasut 提交于
The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
-
由 Marek Vasut 提交于
Add ECSPI clock entries to iMX8MN clock driver. Only make those entries available in case SPI support in U-Boot is enabled at all to conserve space, esp. in SPL. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
-
由 Adam Ford 提交于
The i.MX8M Mini can use the FlexSPI driver. Add support for it to the driver. Signed-off-by: NAdam Ford <aford173@gmail.com>
-
由 Heiko Schocher 提交于
prevent unsued variable compiler warning if DM_REGULATOR is not set. Signed-off-by: NHeiko Schocher <hs@denx.de>
-
由 Martin Fuzzey 提交于
Now that header files no longer include common.h it must be included first. Otherwise the build fails with errors like include/asm/arch/clock.h:43:1: error: unknown type name 'u32' u32 imx_get_uartclk(void); Fixes: c3dc39a2 ("arm: Don't include common.h in header files") Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Peng Fan 提交于
Move SP to end of OCRAM space. Drop MALLOC_F to make it alloc from stack space. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
-
由 Ye Li 提交于
When doing DDR scrub, the DDR may enter into self refresh if the selfref_en is enabled before DDR scrub. This will cause scrub can't complete that SBRSTAT.scrub_done won't be set. Since the selfref_en can be programmed during the course of normal operation, move it after DDR scrub Signed-off-by: NYe Li <ye.li@nxp.com> Acked-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
-
- 22 1月, 2021 7 次提交
-
-
由 Claudiu Beznea 提交于
Take into account all RGMII interface types. Depending on it the RGMII PHY's timings are setup. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
-
由 Claudiu Beznea 提交于
Add support for SAMA7G5 EMAC. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
-
由 Claudiu Beznea 提交于
Add support for SAMA7G5 GMAC. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
-
由 Claudiu Beznea 提交于
clk_set_rate() returns the set rate in case of success and a negative number in case of failure. Consider failure only the negative numbers. Fixes: 3ef64444 ("dm: net: macb: Implement link speed change callback") Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
-
由 Claudiu Beznea 提交于
Different implementation of USER IO register needs different mapping for bit fields of this register. Add implementation for this and, since clken is part of USER IO and it needs to be activated based on per SoC capabilities, add caps in macb_config where clken specific information needs to be filled. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
-
由 Eugen Hristev 提交于
Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>
-
由 Eugen Hristev 提交于
Use dev_read_prop instead of using the fdt_read_property which reads from the GD struct's fdt. This way the node is accessed via the device config instead of the global struct, which makes code more portable and GD independent. Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>
-
- 21 1月, 2021 2 次提交
-
-
由 Shawn Lin 提交于
Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
-
由 Shawn Lin 提交于
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as part of Generic PHY framework. Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
-