By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NStefan Roese <sr@denx.de>

At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NStefan Roese <sr@denx.de>

It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NStefan Roese <sr@denx.de>

This is not used by any board. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Clean up board_f sequence a little
This series tries to remove #ifdefs from the board_f init sequence. It
gets as far as I2C and then we need to discuss whether we can start to
remove the old I2C framework.

I think that ideally each entry in the init sequence should be enabled by
at most one CONFIG, which is in Kconfig and is not arch-specific.
END
Acked-by: NLukasz Majewski <lukma@denx.de>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>

There is no good reason to use a different name on PowerPC. Change it to
timer_init() like the others.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NStefan Roese <sr@denx.de>

The OpenRISC architecture is currently unmaintained, remove.

Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: NTom Rini <trini@konsulko.com>

The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.

Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
[squash the commits, update the commit message]
Signed-off-by: NJagan Teki <jagan@openedev.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: NSimon Glass <sjg@chromium.org>

This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.

The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality.

For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.

The following functionality is working so far:
- eMMC boot, environment storage and Toradex factory config block
- Gigabit Ethernet
- MMC/SD cards (both MMC1 as well as SD1 slot)
- USB client/host (dual role OTG port as client e.g. for DFU/UMS or host,
  other two ports as host)
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit
compared t previous implementation.

In particular:
 * We used to have a generic START bit for all cores selected by CORE_SEL
   mask. But now we don't touch CORE_SEL at all because we have a dedicated
   START bit for each core:
     bit 0: Core 0 (master)
     bit 1: Core 1 (slave)
 * Now there's no need to select "manual" mode of core start

Additional challenge for us is how to tell which axs103 firmware we're
dealing with. For now we'll rely on ARC core version which was bumped
from 2.1c to 3.0.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

 * Rely on default pulse polarity value
 * Don't mess with "multicore" value as it doesn't affect execution

In essence we now do a bare minimal stuff:
 1) Select HS38x2_1 with CORE_SEL=1 bits
 2) Select "manual" core start (via CREG) with START_MODE=0
 3) Generate cpu_start pulse with START=1
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.

Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.

So this commit is the first step on the road to unified device tree blobs.

First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.

Also we delete axs10x.dts as it is no longer used.

One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.
Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.

It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.

On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: NMario Six <mario.six@gdsys.cc>
Signed-off-by: NStefan Roese <sr@denx.de>

This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.
Signed-off-by: NStefan Roese <sr@denx.de>

Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).

In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Fix the default pin control values in a board-specific
function on early board init stage.
This fix allows the NETA driver to work in RGMII
mode until the full-featured pin control driver gets
introduced.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can be used. The latter feature is called IE Key Extension
Feature.

For Layerscape Chasis 3 based platforms, IE table is validated by
Bootrom and address of this table is written in scratch registers 13
and 14 via PBI commands.

Following are the steps describing usage of this feature:

1) Verify IE Table in ISBC phase using keys stored in fuses.
2) Install IE table. (To be used across verification of multiple
   images stored in a static global structure.)
3) Use keys from IE table, to verify further images.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Moved the ifdef into ppa.h and removed the duplicated macros.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Moves sec_init to board_init rather than in misc_init function beacuse
PPA will be initialised in board_init function and for PPA validation
sec_init has to be done prior to PPA init.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: NKen Lin <yungching0725@gmail.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Acked-by: NIan Ray <ian.ray@ge.com>

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: NKen Lin <yungching0725@gmail.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Acked-by: NIan Ray <ian.ray@ge.com>

We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.

Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.

So this commit is the first step on the road to unified device tree blobs.

First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.

Also we delete axs10x.dts as it is no longer used.

One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.
Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.

It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.

On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: NMario Six <mario.six@gdsys.cc>
Signed-off-by: NStefan Roese <sr@denx.de>

This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.
Signed-off-by: NStefan Roese <sr@denx.de>

Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).

In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Fix the default pin control values in a board-specific
function on early board init stage.
This fix allows the NETA driver to work in RGMII
mode until the full-featured pin control driver gets
introduced.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>