board_f: Drop setup_dram_config() wrapper

By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NStefan Roese <sr@denx.de>

arch/arm/cpu/arm926ejs/armada100/dram.c

@@ -108,7 +108,9 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	dram_init();
+
+	return 0;
 }

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -663,7 +663,7 @@ phys_size_t get_effective_memsize(void)
 	return ea_size;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 	phys_size_t dp_ddr_size;
@@ -772,6 +772,8 @@ void dram_init_banksize(void)
 		}
 	}
 #endif
+
+	return 0;
 }
 
 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)

arch/arm/include/asm/u-boot-arm.h

@@ -36,7 +36,7 @@ int	arch_early_init_r(void);
 
 /* board/.../... */
 int	board_init(void);
-void	dram_init_banksize (void);
+int dram_init_banksize(void);
 void	board_quiesce_devices(void);
 
 /* cpu/.../interrupt.c */

arch/arm/mach-davinci/misc.c

@@ -28,10 +28,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 #endif
 

arch/arm/mach-meson/board.c

@@ -34,11 +34,13 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve first 16 MiB of RAM for firmware */
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
 	gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)

arch/arm/mach-mvebu/arm64-common.c

@@ -82,7 +82,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	const void *fdt = gd->fdt_blob;
 	const fdt32_t *val;
@@ -90,13 +90,13 @@ void dram_init_banksize(void)
 
 	val = get_memory_reg_prop(fdt, &len);
 	if (len < 0)
-		return;
+		return -ENXIO;
 
 	ac = fdt_address_cells(fdt, 0);
 	sc = fdt_size_cells(fdt, 0);
 	if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
 		printf("invalid address/size cells\n");
-		return;
+		return -ENXIO;
 	}
 
 	cells = ac + sc;
@@ -114,6 +114,8 @@ void dram_init_banksize(void)
 		      i, (unsigned long)gd->bd->bi_dram[i].start,
 		      (unsigned long)gd->bd->bi_dram[i].size);
 	}
+
+	return 0;
 }
 
 int arch_cpu_init(void)

arch/arm/mach-mvebu/dram.c

@@ -273,7 +273,7 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	u64 size = 0;
 	int i;
@@ -287,6 +287,8 @@ void dram_init_banksize(void)
 		if (size > SDRAM_SIZE_MAX)
 			mvebu_sdram_bs_set(i, 0x40000000);
 	}
+
+	return 0;
 }
 
 #if defined(CONFIG_ARCH_MVEBU)

arch/arm/mach-omap2/am33xx/emif4.c

@@ -32,10 +32,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 

arch/arm/mach-omap2/omap3/emif4.c

@@ -142,7 +142,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	unsigned int size0 = 0, size1 = 0;
 
@@ -153,6 +153,8 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
 }
 
 /*

arch/arm/mach-omap2/omap3/sdrc.c

@@ -216,7 +216,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	unsigned int size0 = 0, size1 = 0;
 
@@ -227,6 +227,8 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
 }
 
 /*

arch/arm/mach-orion5x/dram.c

@@ -42,7 +42,7 @@ int dram_init (void)
 	return 0;
 }
 
-void dram_init_banksize (void)
+int dram_init_banksize(void)
 {
 	int i;
 
@@ -52,4 +52,6 @@ void dram_init_banksize (void)
 			(long *) (gd->bd->bi_dram[i].start),
 			CONFIG_MAX_RAM_BANK_SIZE);
 	}
+
+	return 0;
 }

arch/arm/mach-tegra/board2.c

@@ -315,7 +315,7 @@ static ulong usable_ram_size_below_4g(void)
  * start address of that bank cannot be represented in the 32-bit .size
  * field.
  */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
@@ -334,6 +334,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].start = 0;
 		gd->bd->bi_dram[1].size = 0;
 	}
+
+	return 0;
 }
 
 /*

arch/arm/mach-tegra/tegra186/nvtboot_mem.c

@@ -72,7 +72,7 @@ int dram_init(void)
 
 extern unsigned long nvtboot_boot_x0;
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i;
 
@@ -80,6 +80,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = ram_banks[i].start;
 		gd->bd->bi_dram[i].size = ram_banks[i].size;
 	}
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)

arch/arm/mach-uniphier/dram_init.c

@@ -232,7 +232,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	struct uniphier_dram_map dram_map[3] = {};
 	int i;
@@ -246,6 +246,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = dram_map[i].base;
 		gd->bd->bi_dram[i].size = dram_map[i].size;
 	}
+
+	return 0;
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP

arch/x86/cpu/broadwell/sdram.c

@@ -28,9 +28,11 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	mrc_common_dram_init_banksize();
+
+	return 0;
 }
 
 void broadwell_fill_pei_data(struct pei_data *pei_data)

arch/x86/cpu/coreboot/sdram.c

@@ -104,7 +104,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i, j;
 
@@ -121,4 +121,6 @@ void dram_init_banksize(void)
 			}
 		}
 	}
+
+	return 0;
 }

arch/x86/cpu/efi/sdram.c

@@ -22,8 +22,10 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = efi_get_ram_base();
 	gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
+
+	return 0;
 }

arch/x86/cpu/ivybridge/sdram.c

@@ -46,9 +46,11 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	mrc_common_dram_init_banksize();
+
+	return 0;
 }
 
 static int read_seed_from_cmos(struct pei_data *pei_data)

arch/x86/cpu/qemu/dram.c

@@ -26,10 +26,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*

arch/x86/cpu/quark/dram.c

@@ -162,10 +162,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*

arch/x86/include/asm/u-boot-x86.h

@@ -41,7 +41,7 @@ void x86_disable_caches(void);
 int x86_init_cache(void);
 void reset_cpu(ulong addr);
 ulong board_get_usable_ram_top(ulong total_size);
-void dram_init_banksize(void);
+int dram_init_banksize(void);
 int default_print_cpuinfo(void);
 
 /* Set up a UART which can be used with printch(), printhex8(), etc. */

arch/x86/lib/efi/efi.c

@@ -92,7 +92,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	struct efi_mem_desc *desc, *end;
 	struct efi_entry_memmap *map;
@@ -103,7 +103,7 @@ void dram_init_banksize(void)
 	if (ret) {
 		/* We should have stopped in dram_init(), something is wrong */
 		debug("%s: Missing memory map\n", __func__);
-		return;
+		return -ENXIO;
 	}
 	end = (struct efi_mem_desc *)((ulong)map + size);
 	desc = map->desc;
@@ -123,6 +123,8 @@ void dram_init_banksize(void)
 			EFI_PAGE_SHIFT;
 		num_banks++;
 	}
+
+	return 0;
 }
 
 int checkcpu(void)

arch/x86/lib/fsp/fsp_dram.c

@@ -41,10 +41,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 /*

board/AndesTech/adp-ag101p/adp-ag101p.c

@@ -49,12 +49,14 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
 	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bd)

board/armadeus/apf27/apf27.c

@@ -193,7 +193,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = get_ram_size((void *)PHYS_SDRAM_1,
@@ -204,6 +204,8 @@ void dram_init_banksize(void)
 					     PHYS_SDRAM_2_SIZE);
 	else
 		gd->bd->bi_dram[1].size = 0;
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)

board/armltd/vexpress/vexpress_common.c

@@ -109,7 +109,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size =
@@ -117,6 +117,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size =
 			get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
 }
 
 /*

board/armltd/vexpress64/vexpress64.c

@@ -70,7 +70,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -78,6 +78,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 #endif
+
+	return 0;
 }
 
 /*

board/beckhoff/mx53cx9020/mx53cx9020.c

@@ -86,13 +86,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 u32 get_board_rev(void)

board/broadcom/bcm23550_w1d/bcm23550_w1d.c

@@ -62,10 +62,12 @@ int dram_init(void)
 }
 
 /* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 #ifdef CONFIG_MMC_SDHCI_KONA

board/broadcom/bcm28155_ap/bcm28155_ap.c

@@ -69,10 +69,12 @@ int dram_init(void)
 }
 
 /* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 #ifdef CONFIG_MMC_SDHCI_KONA

board/broadcom/bcm_ep/board.c

@@ -37,10 +37,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 int board_early_init_f(void)

board/broadcom/bcmns2/northstar2.c

@@ -43,13 +43,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)

board/cadence/xtfpga/xtfpga.c

@@ -48,10 +48,12 @@ int checkboard(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 int board_postclk_init(void)

board/cirrus/edb93xx/edb93xx.c

@@ -216,9 +216,11 @@ static unsigned dram_init_banksize_int(int print)
 	return dram_total;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	dram_init_banksize_int(0);
+
+	return 0;
 }
 
 /* called in board_init_f (before relocation) */

board/compulab/cm_fx6/cm_fx6.c

@@ -688,7 +688,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
@@ -720,6 +720,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = 0x7FF00000;
 		break;
 	}
+
+	return 0;
 }
 
 int dram_init(void)

board/denx/m53evk/m53evk.c

@@ -59,13 +59,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 static void setup_iomux_uart(void)

board/esd/meesc/meesc.c

@@ -132,10 +132,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)

board/freescale/ls1021aqds/ddr.c

@@ -184,8 +184,10 @@ int initdram(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }

board/freescale/mx35pdk/mx35pdk.c

@@ -47,13 +47,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)

board/freescale/mx53ard/mx53ard.c

@@ -32,13 +32,15 @@ int dram_init(void)
 
 	return 0;
 }
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_NAND_MXC

board/freescale/mx53loco/mx53loco.c

@@ -58,13 +58,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 u32 get_board_rev(void)

board/freescale/mx53smd/mx53smd.c

@@ -30,13 +30,15 @@ int dram_init(void)
 
 	return 0;
 }
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \

board/hisilicon/hikey/hikey.c

@@ -410,7 +410,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/*
 	 * Reserve regions below from DT memory node (which gets generated
@@ -442,6 +442,8 @@ void dram_init_banksize(void)
 
 	gd->bd->bi_dram[5].start = 0x22000000;
 	gd->bd->bi_dram[5].size = 0x1c000000;
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)

board/mini-box/picosam9g45/picosam9g45.c

@@ -283,7 +283,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
@@ -291,6 +291,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 							PHYS_SDRAM_2_SIZE);
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R

board/qualcomm/dragonboard410c/dragonboard410c.c

@@ -19,10 +19,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 

board/rockchip/evb_rk3328/evb-rk3328.c

@@ -22,11 +22,13 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve 0x200000 for ATF bl31 */
 	gd->bd->bi_dram[0].start = 0x200000;
 	gd->bd->bi_dram[0].size = 0x7e000000;
+
+	return 0;
 }
 
 int usb_gadget_handle_interrupts(void)

board/rockchip/evb_rk3399/evb-rk3399.c

@@ -67,9 +67,11 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/* Reserve 0x200000 for ATF bl31 */
 	gd->bd->bi_dram[0].start = 0x200000;
 	gd->bd->bi_dram[0].size = 0x7e000000;
+
+	return 0;
 }

board/ronetix/pm9261/pm9261.c

@@ -264,10 +264,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R

board/ronetix/pm9263/pm9263.c

@@ -360,10 +360,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R

board/ronetix/pm9g45/pm9g45.c

@@ -144,10 +144,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R

board/samsung/arndale/arndale.c

@@ -55,7 +55,7 @@ int power_init_board(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i;
 	u32 addr, size;
@@ -67,6 +67,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = addr;
 		gd->bd->bi_dram[i].size = size;
 	}
+
+	return 0;
 }
 
 #ifdef CONFIG_GENERIC_MMC

board/samsung/common/board.c

@@ -108,7 +108,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	unsigned int i;
 	unsigned long addr, size;
@@ -120,6 +120,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = addr;
 		gd->bd->bi_dram[i].size = size;
 	}
+
+	return 0;
 }
 
 static int board_uart_init(void)

board/samsung/goni/goni.c

@@ -52,7 +52,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -60,6 +60,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_DISPLAY_BOARDINFO

board/samsung/smdkc100/smdkc100.c

@@ -51,10 +51,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_DISPLAY_BOARDINFO

board/samsung/smdkv310/smdkv310.c

@@ -52,7 +52,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
@@ -66,6 +66,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 							PHYS_SDRAM_4_SIZE);
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)

board/spear/common/spr_misc.c

@@ -33,10 +33,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 int board_early_init_f()

board/st/stih410-b2260/board.c

@@ -16,10 +16,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 int board_init(void)

board/st/stv0991/stv0991.c

@@ -93,10 +93,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_CMD_NET

board/ti/dra7xx/evm.c

@@ -498,7 +498,7 @@ int board_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	u64 ram_size;
 
@@ -510,6 +510,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].start = 0x200000000;
 		gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 	}
+
+	return 0;
 }
 
 int board_late_init(void)

board/xilinx/microblaze-generic/microblaze-generic.c

@@ -25,10 +25,12 @@ static int reset_pin = -1;
 
 ulong ram_base;
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = ram_base;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
+
+	return 0;
 }
 
 int dram_init(void)

board/xilinx/zynq/board.c

@@ -130,9 +130,11 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	fdtdec_setup_memory_banksize();
+
+	return 0;
 }
 
 int dram_init(void)

board/xilinx/zynqmp/zynqmp.c

@@ -180,9 +180,11 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	fdtdec_setup_memory_banksize();
+
+	return 0;
 }
 
 int dram_init(void)

board/zipitz2/zipitz2.c

@@ -69,10 +69,12 @@ void usb_board_stop(void)
 }
 #endif
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef	CONFIG_CMD_MMC

common/board_f.c

@@ -208,12 +208,14 @@ static int show_dram_config(void)
 	return 0;
 }
 
-__weak void dram_init_banksize(void)
+__weak int dram_init_banksize(void)
 {
 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
 #endif
+
+	return 0;
 }
 
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
@@ -644,14 +646,6 @@ static int init_post(void)
 }
 #endif
 
-static int setup_dram_config(void)
-{
-	/* Ram is board specific, so move it to board code ... */
-	dram_init_banksize();
-
-	return 0;
-}
-
 static int reloc_fdt(void)
 {
 #ifndef CONFIG_OF_EMBED
@@ -891,7 +885,7 @@ static const init_fnc_t init_sequence_f[] = {
 	reserve_fdt,
 	reserve_arch,
 	reserve_stacks,
-	setup_dram_config,
+	dram_init_banksize,
 	show_dram_config,
 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
 	defined(CONFIG_SH)