Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the DRAM controller initialisation for the RK3188, RK3288
and RK3399... all of these read some of the tuning/setup/timing
parameters from the device-tree.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Since this driver can be used for rk8xx series pmic,
let's rename rk808 to rk8xx, to make it clear.

Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./`
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>

The sdram IP blocks used on rk3066, rk3188 and rk3288 are very similar
and we want to unify things once all 3 work as expected.
Therefore try to keep the rk3288 sdram driver in line by applying the
general review comments received for the rk3188 variant to it as well.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Use defines to describe the bit shifts used to create the
table for ddrconf register values.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add support for rk3288 dram capacity auto detect, support DDR3 and
LPDDR3, DDR2 is not supported.
The program will automatically detect:
- channel number
- rank number
- column address number
- row address number

The dts file do not need to describe those info after apply this patch.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NSimon Glass <sjg@chromium.org>
Tested-by: NVagrant Cascadian <vagrant@debian.org>
Tested-by: NVagrant Cascadian <vagrant@debian.org>

The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.

This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.
Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects
the bootloader to store the necessary information there.  We're using
the same register to pass the same information between the SPL and
U-Boot but in a slightly different format.

Change this to use the format expected by the Linux DMC driver so that
the system doesn't hang in Linux by misconfiguring the RAM.

This is almost the same as commit b5788dc0 ("rockchip: rk3288: correct
sdram setting") which was reverted in commit b525556e ("Revert "rockchip:
rk3288: correct sdram setting"") but parenthese have been added to apply
the mask correctly when reading the "bw" setting and a couple of minor
style issues have been fixed to keep check_patch.pl happy.
Signed-off-by: NJohn Keeping <john@metanate.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.

Fix this by calling rockchip_get_clk() instead.

Fixes: 135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NAnatolij Gustschin <agust@denx.de>

The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Add support for of-platdata with rk3288 SDRAM initr. This requires decoding
the of-platdata struct and setting up the device from that. Also the driver
needs to be renamed to match the string that of-platdata will search for.

The platform data is copied from the of-platdata structure to the one used
by the driver. This allows the same code to be used with device tree and
of-platdata.
Signed-off-by: NSimon Glass <sjg@chromium.org>

It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Note that only SPL needs to fiddle with
the SDRAM registers, so decoding the platform data fully is not necessary in
U-Boot proper.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This reverts commit b5788dc0.

Ram size is incorrectly reported as 512MB on a firefly-rk3288 board
with 2GB of ram. Reverting this patch displays the full amount of ram.
Signed-off-by: NVagrant Cascadian <vagrant@debian.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Use this new function in places where it simplifies the code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
and it expects uboot to store the value using a same protocol. But now
the ddr setting value is different with DMC, so if you enable the DMC,
system would crash in kernel. Correct the sdram setting here, according
to the requirements of kernel.

[0]
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/
chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: NSimon Glass <sjg@chromium.org>

This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix spaces in two comments in this file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Use this function in preference to the macro.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.
Signed-off-by: NSimon Glass <sjg@chromium.org>