- 11 7月, 2017 3 次提交
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由 Wadim Egorov 提交于
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. The module can be connected to different carrier boards. It can be also equipped with different RAM, SPI flash and eMMC variants. The Rapid Development Kit option is using the following setup: - 1 GB DDR3 RAM (2 Banks) - 1x 4 KB EEPROM - DP83867 Gigabit Ethernet PHY - 16 MB SPI Flash - 4 GB eMMC Flash Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination with the phyCORE-RK3288 System on Module. Signed-off-by: NWadim Egorov <w.egorov@phytec.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Replace the sdram_init() in board init and rockchip_sdram_size() in sdram driver for all the Rockchip SoCs which enable CONFIG_RAM. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Make dram_init() in rk3036-board.c conditional on CONFIG_RAM: Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Philipp Tomsich 提交于
With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the DRAM controller initialisation for the RK3188, RK3288 and RK3399... all of these read some of the tuning/setup/timing parameters from the device-tree. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 11 5月, 2017 1 次提交
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由 Jacob Chen 提交于
Since this driver can be used for rk8xx series pmic, let's rename rk808 to rk8xx, to make it clear. Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./` Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
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- 05 4月, 2017 2 次提交
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由 Jernej Skrabec 提交于
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC, micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and expansion ports. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NEddie Cai <eddie.cai.linux@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Jernej Skrabec 提交于
Sort rk3288 boards in alphabetical order. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NEddie Cai <eddie.cai.linux@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 17 3月, 2017 2 次提交
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由 Heiko Stübner 提交于
The sdram IP blocks used on rk3066, rk3188 and rk3288 are very similar and we want to unify things once all 3 work as expected. Therefore try to keep the rk3288 sdram driver in line by applying the general review comments received for the rk3188 variant to it as well. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
Use defines to describe the bit shifts used to create the table for ddrconf register values. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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- 10 2月, 2017 1 次提交
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由 Eddie Cai 提交于
Miniarm is the internal project code. Now it is officially named Tinker board. So rename it. Signed-off-by: NEddie Cai <eddie.cai@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 08 2月, 2017 1 次提交
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由 Simon Glass 提交于
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 24 1月, 2017 1 次提交
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由 Tom Rini 提交于
This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: NTom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
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- 12 1月, 2017 1 次提交
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由 Martin Michlmayr 提交于
The veyron-minnie Kconfig referred to jerry by mistake. Signed-off-by: NMartin Michlmayr <tbm@cyrius.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 26 11月, 2016 3 次提交
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由 Simon Glass 提交于
This adds support for the Asus Chromebook Flip, an RK3288-based clamshell device which can flip into 'tablet' mode. The device tree file comes from Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This adds support for the Asus Chromebit, and RK3288-based device designed to plug directly into an HDMI monitor. The device tree file comes from Linux v4.8. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
At present we have a single rk3288-based Chromebook: chromebook_jerry. But all such Chromebooks can use the same binary with only device-tree differences. The family name is 'veyron', so rename the files accordingly. Also update the device-tree filename since this currently differs from Linux. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 31 10月, 2016 4 次提交
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由 Kever Yang 提交于
SPL_MMC_SUPPORT defined in rockchip top level Kconfig instead of inside rk3288 and default to disable if ROCKCHIP_SPL_BACK_TO_BROM defined. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Add support for rk3288 dram capacity auto detect, support DDR3 and LPDDR3, DDR2 is not supported. The program will automatically detect: - channel number - rank number - column address number - row address number The dts file do not need to describe those info after apply this patch. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Tested-by: NSimon Glass <sjg@chromium.org> Tested-by: NVagrant Cascadian <vagrant@debian.org> Tested-by: NVagrant Cascadian <vagrant@debian.org>
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由 Kever Yang 提交于
The GRF base address is missing, fix it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Simon Glass 提交于
This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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- 02 10月, 2016 1 次提交
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由 Xu Ziyuan 提交于
The all current Rockchip SoCs supporting 4GB of ram have problems accessing the memory region 0xfe000000~0xff000000. Actually, some IP controller can't address to, so let's limit the available range. This patch fixes a bug which found in miniarm-rk3288-4GB board. The U-Boot was relocated to 0xfef72000, and .bss variants was also relocated, such as do_fat_read_at_block. Once eMMC controller transfer data to do_fat_read_at_block via DMA, DMAC can't access more than 0xfe000000. So that DMAC didn't work sane. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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- 22 9月, 2016 1 次提交
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由 Kever Yang 提交于
We do some SoC level one time setting initialization in arch_cpu_init. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 17 9月, 2016 5 次提交
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 12 8月, 2016 1 次提交
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由 Max Filippov 提交于
Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 06 8月, 2016 1 次提交
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由 Xu Ziyuan 提交于
Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 31 7月, 2016 3 次提交
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由 jk.kernel@gmail.com 提交于
PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is the real vendor name. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 26 7月, 2016 5 次提交
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由 John Keeping 提交于
The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects the bootloader to store the necessary information there. We're using the same register to pass the same information between the SPL and U-Boot but in a slightly different format. Change this to use the format expected by the Linux DMC driver so that the system doesn't hang in Linux by misconfiguring the RAM. This is almost the same as commit b5788dc0 ("rockchip: rk3288: correct sdram setting") which was reverted in commit b525556e ("Revert "rockchip: rk3288: correct sdram setting"") but parenthese have been added to apply the mask correctly when reading the "bw" setting and a couple of minor style issues have been fixed to keep check_patch.pl happy. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The current code picks the first available clock. In U-Boot proper this is the oscillator device, not the SoC clock device. As a result the HDMI display does not work. Fix this by calling rockchip_get_clk() instead. Fixes: 135aa950 (clk: convert API to match reset/mailbox style) Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NAnatolij Gustschin <agust@denx.de>
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由 Simon Glass 提交于
On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 15 7月, 2016 3 次提交
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由 Simon Glass 提交于
Add support for of-platdata with rk3288 SDRAM initr. This requires decoding the of-platdata struct and setting up the device from that. Also the driver needs to be renamed to match the string that of-platdata will search for. The platform data is copied from the of-platdata structure to the one used by the driver. This allows the same code to be used with device tree and of-platdata. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Note that only SPL needs to fiddle with the SDRAM registers, so decoding the platform data fully is not necessary in U-Boot proper. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The syscon devices all end up having diffent driver names with of-platdata, since the driver name comes from the first string in the compatible list. Add separate device declarations for each one, and add a bind method to set up driver_data correctly. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 20 6月, 2016 1 次提交
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由 Stephen Warren 提交于
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org>
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