- 11 7月, 2017 40 次提交
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由 Sjoerd Simons 提交于
Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 boards, using the RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO. Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: NRomain Perier <romain.perier@collabora.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Use fixed regulator for sdmmc-pwren for sdmmc power. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Wadim Egorov 提交于
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. The module can be connected to different carrier boards. It can be also equipped with different RAM, SPI flash and eMMC variants. The Rapid Development Kit option is using the following setup: - 1 GB DDR3 RAM (2 Banks) - 1x 4 KB EEPROM - DP83867 Gigabit Ethernet PHY - 16 MB SPI Flash - 4 GB eMMC Flash Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination with the phyCORE-RK3288 System on Module. Signed-off-by: NWadim Egorov <w.egorov@phytec.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Meng Dongyang 提交于
Add fixed regulator for the port of typec0 and typec1 to control vbus instead of gpio. Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Meng Dongyang 提交于
Enable dwc2 controller and add fixed regulator for dwc2 controller to control vbus. Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Meng Dongyang 提交于
The driver changes gpio to fixed regulator to control vbus, so add fixed regulator node in DTS for xhci driver. Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Rockchip using the same bit definition for dram info and write to os_reg, the col and bw info is not correct and let's fix it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 eric.gao@rock-chips.com 提交于
According to rk3288 spec, the pwm register order is: PWM_PWM0_CNT, PWM_PWM0_PERIOD_HPR, PWM_PWM0_DUTY_LPR, PWM_PWM0_CTRL but the source code's order is: struct rk3288_pwm { u32 cnt; u32 duty_lpr; u32 period_hpr; u32 ctrl; }; So, correct it here. It is the same as RK3399. Signed-off-by: NEric Gao <eric.gao@rock-chips.com> Edited the commit message: Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Enable sdmmc device and add the spl boot device sequence. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Since the 'clock-freq-min-max' is deprecated, we use max-frequency. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Since the 'clock-freq-min-max' is deprecated, we use max-frequency. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Since the 'clock-freq-min-max' is deprecated, we use max-frequency. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
evb_rk3229 is a RK3229 based board, with: - 8GB eMMC; - 1GB DDR SDRAM; - 2 USB2.0 HOST port; - 1 MAC port; - 1 HDMI port; - IR; - WiFi; Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Enable soc support for SPL and U-boot skeleton. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
The dts files are from kernel and with modify to adapt U-Boot. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add init pinctrl driver support for: - i2c; - spi; - uart; - pwm; - emmc/sdmmc; Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add clock driver init support for: - cpu, bus clock init; - emmc, sdmmc clock; - ddr clock; Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed format specified (%x -> %p) in clk_rk322x.c: Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
The bank0 ram size should be the DRAM size minus reserved size, the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399: Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add dmc node to enable sdram driver. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add a dmc node for sdram driver. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add sdram driver in U-Boot for get the correct sdram size from sys_reg, so that U-Boot can co-work with Rockchip loader or SPL to get different dram capability and then tell the kernel. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add sdram driver in U-Boot for get the correct sdram size from sys_reg, so that U-Boot can co-work with Rockchip loader or SPL to get different dram capability and then tell the kernel. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Replace the sdram_init() in board init and rockchip_sdram_size() in sdram driver for all the Rockchip SoCs which enable CONFIG_RAM. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Make dram_init() in rk3036-board.c conditional on CONFIG_RAM: Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
There are some functions like sdram_size_mb can be re-used for different rockchip SoCs, just put them into common file. Add board_get_usable_ram_top() for ram_top init base on SDRAM_MAX_SIZE. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Added SDRAM_MAX_SIZE definition for RK3036: Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> fixup: 3036 fix for sdram_common
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由 Kever Yang 提交于
According to rk3328 TRM: 0~0xff000000 is ddr space; 0xff000000~0xffffffff is device space. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Philipp Tomsich 提交于
With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the DRAM controller initialisation for the RK3188, RK3288 and RK3399... all of these read some of the tuning/setup/timing parameters from the device-tree. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andrew F. Davis 提交于
The size of the secure image does not include the size of the header, subtract this out before we move the image or we grab extra data after the image. Signed-off-by: NAndrew F. Davis <afd@ti.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
gpio2 is used to detect lcd based on which pin mux is done in SPL. gpio7 is used to enable vtt regulator. Enable these two gpio nodes in SPL. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Enable spl_early_init() so that spl can use DT very early during boot. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
ROM stores the boot params information in a known location and passes it to SPL. This information needs to be copied very early during boot or else there is a chance of getting corrupted by SPL. So move this boot device detection very early during boot. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jorge Ramirez-Ortiz 提交于
This port adds support for: 1) Serial 2) eMMC 3) USB It has been tested with ARM TRUSTED FIRMWARE running u-boot as the BL33 executable [see board's README] eMMC has been tested for reading and booting the loader and linux kernels as well as saving the u-boot environment. USB has been tested with ASIX networking adapter and SanDisk 7.4GB drive. PSCI has been tested via the reset call (PSCI executes from DDR) The firwmare upgrade process has been tested via TFTP and USB FAT filesystem containing the fastboot.bin image in one of the partitions. Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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由 Jorge Ramirez-Ortiz 提交于
Pulled from Linux 4.12-rc3 Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Cooper Jr., Franklin 提交于
Add basic DT support for K2G ICE evm. Only minimal peripherals are supported to allow console output and MMC boot. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
Disable netcp by default like all other peripherals in the dtsi file. Enable the peripheral explicitly in the board specific dts file. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
Upstream Linux has the unit address being added to the various 66AK2Gx boards dts. Therefore, update the dts to mimic this change. Also remove memory node from the base K2G dtsi file. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
Adding the unit address to the memory node was causing the below error: Warning (reg_format): "reg" property in /memory has invalid length (8 bytes) (#address-cells == 2, #size-cells == 2) Further debugging showed that this was due to the memory node added by default to skeleton.dtsi which was being included in keystone-k2g.dtsi. Adding a missing node was all that was needed to remove this deprecated dtsi file from the SoC dtsi. With skeleton.dtsi removed the dtc compiler no longer complained about including the unit address for the memory node. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
Different K2G evms may need to program the various KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to properly program the register. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
K2G GP doesn't require the MR2 register to be programed since the default is good enough. However, newer K2G boards do need to change this register value. Therefore, instead of not writing this register if ran on a K2G board just program the value to be written to match the default/reset value. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
Future boards will need to configure DDR3 registers in a slightly different manner. Support this by defining additional variables and defines that will be utilized later. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Cooper Jr., Franklin 提交于
u-boot.bin is a copy of: u-boot-fit-dtb.bin if CONFIG_FIT_EMBED is enabled, u-boot-dtb.bin if CONFIG_OF_SEPARATE is enabled, u-boot-nodtb.bin if DT is not enabled. So, use u-boot.bin to to generate keystone images instead of u-boot-dtb.bin Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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