- 28 9月, 2016 1 次提交
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由 Sriram Dash 提交于
The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
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- 26 1月, 2016 1 次提交
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由 Prabhakar Kushwaha 提交于
Users migrating Freescale's PowerPC SoC U-Boot code to their custom board, often overlook the need to execute set_liodns() and setup_portals() being called by platform files. So Move set_liodns() and setup_portals() to common u-boot boot sequence Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 21 11月, 2014 1 次提交
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由 Simon Glass 提交于
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NAnatolij Gustschin <agust@denx.de>
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- 23 7月, 2014 2 次提交
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由 Shaohui Xie 提交于
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
find_tlb_idx() is called in board_early_init_r() on multiple boards. The return value is not checked before being used to disable a TLB. In normal case the return value wouldn't be -1. In case of a mis- configuration during porting to a new board, checking the return value may be helpful to reveal some user errors. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 06 6月, 2014 1 次提交
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由 Shaohui Xie 提交于
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 25 10月, 2013 1 次提交
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由 Valentin Longchamp 提交于
This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: NYork Sun <yorksun@freescale.com>
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- 21 8月, 2013 2 次提交
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由 Shaohui Xie 提交于
When using QSGMII protocols, the first lane and third lane on each slot need to be swapped. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Acked-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
Since the parameters need to be modified according to different Serdes protocols at runtime, the const will block this. Also remove const from arrays define used by vsc3316_config. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Acked-by: NYork Sun <yorksun@freescale.com>
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- 13 8月, 2013 1 次提交
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由 York Sun 提交于
Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 10 8月, 2013 2 次提交
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由 York Sun 提交于
Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 25 5月, 2013 4 次提交
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由 York Sun 提交于
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ed Swarthout 提交于
Use QIXIS measurement registers to obtain sysclk and ddr clock. This allows using non-standard clock speeds, set by directly writing to clock chip or store the values in qixis clock data eeprom. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 15 5月, 2013 3 次提交
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由 Ed Swarthout 提交于
Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Roy Zang 提交于
Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 04 2月, 2013 1 次提交
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由 Simon Glass 提交于
Move these fields into arch_global_data and tidy up. Signed-off-by: NSimon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 31 1月, 2013 3 次提交
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由 Prabhakar Kushwaha 提交于
Qixis FPGA has tag data contains image name and build date. It is helpful to identify the FPGA image precisely. Signed-off-by: NYork Sun <yorksun@freescale.com> Acked-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaveta Leekha 提交于
This function is called by "qixis_reset switch" command and switch settings are calculated from qixis FPGA registers. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Timur Tabi 提交于
Static variables should be defined in C files, not header files, because otherwise every C file that #includes the header file will generate a duplicate of the variables. Since the vsc3316_xxx[] arrays are only used by t4qds.c anyway, just put the variables there. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 23 10月, 2012 1 次提交
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由 York Sun 提交于
The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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