The function fdt_fixup_dr_usb is specific to fsl/nxp. So,
make the function name explicit and rename fdt_fixup_dr_usb
into fsl_fdt_fixup_dr_usb.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>

Instead of using multiple macros, a data structure is used to pass
board-specific parameters to MMDC DDR driver.
Signed-off-by: NYork Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: NTom Rini <trini@konsulko.com>

Remove unneeded variables and assignments.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NMinkyu Kang <mk7.kang@samsung.com>
Reviewed-by: NAngelo Dureghello <angelo@sysam.it>

LS1046AQDS Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS1046ARDB Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
	 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console
Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.

Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Debug server feature has been dropped from roadmap.
Signed-off-by: NYork Sun <york.sun@nxp.com>

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add this API to make the individual device is able to be set to
the specified permission.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

To be in the safe side we need to enable the CCGR clocks prior
to calling arch_cpu_init().

Inspired by Tim Harvey's commit d783c274 ("imx: ventana: fix boot to SD").
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NEric Nelson <eric@nelint.com>
Tested-by: NEric Nelson <eric@nelint.com>

Adjust DDR3 initialization done in SPL by comparing them against
the NXP DCD table.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NEric Nelson <eric@nelint.com>

When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.

This hang issue does not happen on the NXP U-Boot version.

After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.
Reported-by: NEric Nelson <eric@nelint.com>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NEric Nelson <eric@nelint.com>

Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NEric Nelson <eric@nelint.com>

Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.

Simplify the code by writing directly to this register.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.

Simplify the code by writing directly to this register.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Only a single pad is changed to change sdhc2_dat3 from an
SDIO pin to and from GPIO4:5, so remove the array and use
the imx_iomux_v3_setup_pad() routine.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

mx7dsabresd has two targets:

- mx7dsabresd_defconfig: boots in non-secure mode
- mx7dsabresd_secure_defconfig: boots in secure mode

Print the mode that is being used to help users to easily identify
which target is running on the board.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Most of them are my mistakes.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Update maintainers for secure boot targets.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Add an entry for the mx7dsabresd_secure_defconfig target.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Remove unused define constant.
Signed-off-by: NDiego Dorta <diego.dorta@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
    psci_version,
    psci_features,
    psci_cpu_suspend,
    psci_affinity_info,
    psci_system_reset,
    psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: NWang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add ls1043aqds_lpuart_defconfig to file list.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Add ls2080aqds_qspi_defconfig to file list.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Add SD secure boot target for ls1021atwr.
Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU. Change the u-boot size defined by a
macro for copying the main U-Boot by SPL to also include the u-boot
Secure Boot header size as header is appended to u-boot image. So header
will also be copied from SD to DDR.
Reviewed-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define macros in SPL framework to enable crypto operations.
Reviewed-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40df
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.
Reviewed-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.
Reviewed-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.
Signed-off-by: NVanessa Maegima <vanessa.maegima@nxp.com>

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.
Signed-off-by: NVanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.
Signed-off-by: NVanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>