1. 02 7月, 2015 1 次提交
  2. 26 6月, 2015 2 次提交
  3. 15 6月, 2015 2 次提交
  4. 13 6月, 2015 1 次提交
  5. 01 6月, 2015 1 次提交
  6. 24 4月, 2015 1 次提交
  7. 14 4月, 2015 1 次提交
  8. 30 3月, 2015 1 次提交
  9. 06 1月, 2015 1 次提交
  10. 05 12月, 2014 1 次提交
  11. 24 9月, 2014 1 次提交
    • N
      spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_* · 88e34e5f
      Nikita Kiryanov 提交于
      Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
      SPL. These #defines do not allow the user to select SPI mode for the SPI flash
      (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
      spi_spl_load.c), and duplicate information already provided by
      CONFIG_SF_DEFAULT_* #defines.
      
      Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
      
      Cc: Tom Rini <trini@ti.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
      Cc: Lokesh Vutla <lokeshvutla@ti.com>
      Cc: Vitaly Andrianov <vitalya@ti.com>
      Cc: Lars Poeschel <poeschel@lemonage.de>
      Cc: Bo Shen <voice.shen@atmel.com>
      Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
      Cc: Michal Simek <monstr@monstr.eu>
      Acked-by: NMarek Vasut <marex@denx.de>
      Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
      Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
      88e34e5f
  12. 25 8月, 2014 3 次提交
    • L
      ARM: DRA: Enable VTT regulator · 7b922523
      Lokesh Vutla 提交于
      DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
      and this is controlled by gpio7_11. Configuring gpio7_11.
      The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
      and left unused on previous boards, so it is safe enough to enable gpio
      on all DRA7 boards.
      Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
      7b922523
    • P
      board/ti/dra7xx: add support for parallel NOR · 9352697a
      pekon gupta 提交于
      This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
      The Flash device is connected to GPMC controller on chip-select[0] and accessed
      as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
      is CFI compatible.
      
      As multiple devices are share GPMC pins on this board, so following board
      settings are required to detect NOR device:
           SW5.1 (NAND_BOOTn) = OFF (logic-1)
           SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
           SW5.3 (eMMC_BOOTn) = OFF (logic-1)
           SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      
      And also set appropriate SYSBOOT configurations:
           SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
           SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
           SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
           SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
           SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
           SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
           SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
           SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      
      Also, following changes are required to enable NOR Flash support in
      dra7xx_evm board profile:
      9352697a
    • P
      board/ti/dra7xx: add support for parallel NAND · 54a97d28
      pekon gupta 提交于
      This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
      chip-select[0] on DRA7xx EVM.
      As GPMC pins are shared by multiple devices, so in addition to this patch
      following board settings are required for NAND device detection [1]:
      
        SW5.9 (GPMC_WPN)   = OFF (logic-1)
        SW5.1 (NAND_BOOTn) = ON  (logic-0) /* Active-low */
        SW5.2 (NOR_BOOTn)  = OFF (logic-1)
        SW5.3 (eMMC_BOOTn) = OFF (logic-1)
        SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      
      And also set appropriate SYSBOOT configurations
        SW2.1 (SYSBOOT[0]) = ON  (logic-1) /* selects NAND Boot */
        SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */
        SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */
        SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */
        SW2.5 (SYSBOOT[4]) = ON  (logic-1) /* selects NAND Boot */
        SW2.6 (SYSBOOT[5]) = ON  (logic-1) /* selects NAND Boot */
        SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */
        SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */
      
        SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
        SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
        SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
        SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */
        SW3.5 (SYSBOOT[12])= ON  (logic-1) /* device type: Addr/Data Muxed */
        SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
        SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
        SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      
      Following changes are required in board.cfg to enable NAND on J6-EVM:
      54a97d28
  13. 18 4月, 2014 2 次提交
  14. 04 3月, 2014 1 次提交
  15. 22 2月, 2014 1 次提交
  16. 08 2月, 2014 1 次提交
  17. 25 1月, 2014 1 次提交
  18. 19 12月, 2013 1 次提交
  19. 04 12月, 2013 1 次提交
  20. 02 11月, 2013 1 次提交
  21. 21 10月, 2013 1 次提交
  22. 15 10月, 2013 1 次提交
  23. 07 10月, 2013 1 次提交
  24. 21 9月, 2013 1 次提交
  25. 28 8月, 2013 1 次提交
  26. 16 8月, 2013 1 次提交
    • T
      TI:omap5/dra7xx: Convert to ti_armv7_common.h · a8017574
      Tom Rini 提交于
      Update omap5_common.h to use ti_armv7_common.h, and in turn update
      dra7xx_evm.h and omap5_uevm.h slightly.  The biggest changes here are
      that IP blocks which exist on the platform, and had clocks enabled,
      now have the drivers being built as well.
      Signed-off-by: NTom Rini <trini@ti.com>
      a8017574
  27. 27 7月, 2013 1 次提交
  28. 24 7月, 2013 1 次提交
  29. 18 6月, 2013 1 次提交
  30. 10 6月, 2013 3 次提交
  31. 08 4月, 2013 1 次提交
    • T
      omap5_uevm.h: Move uEVM-specific choices to omap5_uevm.h · 9552ee3e
      Tom Rini 提交于
      The omap5_uevm platform has eMMC, and it makes sense to say that our
      default env storage shall reside there.  Other platforms may not, so
      move this choice to the EVM config.  In addition, we should provide some
      way to partition the flash for later usage, so take advantage of the GPT
      partition table support code and allow that to be setup with some
      reasonable defaults.
      
      Cc: Sricharan R <r.sricharan@ti.com>
      Signed-off-by: NTom Rini <trini@ti.com>
      9552ee3e
  32. 11 3月, 2013 1 次提交
  33. 13 4月, 2010 1 次提交