A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Rename this to be consistent with the change from 'platdata'.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix the condition to set UHS timings for speeds upto HS200.
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Define and use functions for setting input and output tapdelays
based on clk phase delays.
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Define input and output clock phase delays with pre-defined values.

Define arasan_sdhci_clk_data type structure and add it to priv
structure and store these clock phase delays in it.

Read input and output clock phase delays from dt. If these values are
not passed through dt, use pre-defined values.
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Just group macros below headers. Other patches will be using this location
too.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

This reverts commit 942b5fc0.

This is partial revert of the above commit.

mmc_of_parse() is reading no-1-8-v from device tree and if set,
it is clearing the UHS speed capabilities of cfg->host_caps.
cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 |
		    MMC_MODE_HS400 | MMC_MODE_HS400_ES);

This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104,
SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50.

Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(),
these speed flags are getting set again in cfg->host_caps in
sdhci_setup_cfg().

The reason for this is, SDHCI_SUPPORT_XXX flags are cleared
only if controller is not capable of supporting MMC_VDD_165_195 volts.

if (caps & SDHCI_CAN_VDD_180)
	cfg->voltages |= MMC_VDD_165_195;

if (!(cfg->voltages & MMC_VDD_165_195))
	caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
		    SDHCI_SUPPORT_DDR50);

It means "no-1-8-v", which is read from DT is not coming in to effect.
So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to
clear UHS speeds based on no-1-8-v from device tree.

Hence revert the functionality related to no-1-8-v only, rest is fine
in the patch.
Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

Trivial fix.

Fixes: d1f4e39d ("mmc: zynq_sdhci: Add support for SD3.0"
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

DT binding is saying that default value is 0 not -1 that's why fix it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NPeng Fan <peng.fan@nxp.com>

s/xlnx,mio_bank/xlnx,mio-bank/g

DT binding is describing mio-bank not mio_bank that's why fix all DTSes and
also driver itself.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NPeng Fan <peng.fan@nxp.com>

Driver is not calling gd anywhere that's why there is not need to define
it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Move this uncommon header out of the common header.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this header out of the common header.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes
is not evaluated. This results in the bus width staying at its default
value (4 bit in HS200 mode).
Fix this by calling mmc_of_parse. This function also checks for the
"no-1-8-v" and "max-frequency" entries. Remove the handling of those
nodes from this driver.
Signed-off-by: NBenedikt Grassl <Benedikt.Grassl@rohde-schwarz.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

The zynq_sdhci drivers depends on DM_MMC in Kconfig so no need to check for
DM_MMC in the driver so this patch removes it.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Since commit 3d296365 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field. Move the mmc field initialization before sdhci_setup_cfg()
call to avoid crash on mmc pointer dereference.

[this patch is based on commit 41a9fab8 ("mmc: mv_sdhci: fix
uninitialized pointer deref on probe") by Baruch Siach]

Fixes: 3d296365 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: NMatwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu102/zc706)

The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.

Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This variable was incorrectly added by:
"mmc: zynq_sdhci: Add support for SD3.0"
(sha1: d1f4e39d)
which had nothing to do with MMC power sequence provider.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Code around tuning_loop_counter variable expects to go below zero.
That's why this variable can't use unsigned type.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch adds HS200 suuport for ZynqMP and enables
the same for ZC1751 DC1 board which has eMMC on it.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use live-tree functions.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch adds support of SD3.0 for ZynqMP.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: NTom Rini <trini@konsulko.com>

The 'SDHCI_QUIRK_NO_HISPD_BIT' is used wrong here. The purpose of this
quirk is to tell the sdhci-driver that the IP-core doesn't have a "high-
speed-enable" bit in its registers.

With this commit we change this to the correct quirk:
SDHCI_QUIRK_BROKEN_HISPD_MODE
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>

Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -> include/linux/libfdt.h
  include/libfdt_env.h     -> include/linux/libfdt_env.h

and replaces include directives:
  #include <libfdt.h>      -> #include <linux/libfdt.h>
  #include <libfdt_env.h>  -> #include <linux/libfdt_env.h>
Reported-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ
and enabled it in respective defconfig.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: NSimon Glass <sjg@chromium.org>

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The maximum supported peripheral clock frequency of the zynq depends on
the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz
respectively 25 MHz. Use the max-frequency value of the device tree to
determine the maximal supported peripheral clock frequency.
Signed-off-by: NStefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base
clock frequency but this clock is not fixed and depends on the hardware
configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ
doesn't match the real base clock frequency of SDIO_FREQ. Use the clock
framework to determine the frequency at run time.
Signed-off-by: NStefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card interface. Use the same differentiation and allow
the platform to constrain the peripheral interface.
Signed-off-by: NStefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>

"host->version" isn't a SoC specific value.
It doesn't need to get in each SoC drivers.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NMinkyu Kang <mk7.kang@samsung.com>