mmc: zynq_sdhci: Add clock phase delays for Versal
Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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