clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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