- 20 12月, 2016 18 次提交
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由 Nathan Rossi 提交于
The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This board specific implementation uses a static variable 'tmp' which makes these functions unsafe for execution from within the board_init_f context. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Fixes: 8d59d7f6 ("ARM64: zynqmp: Read RAM information from DT") Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This board specific implementation uses a static variable 'tmp' which makes these functions unsafe for execution from within the board_init_f context. This unsafe use of a static variable was causing a specific bug when using the zynq_zybo configuration, U-Boot would generate the following error during image load. This was caused due to dram_init overwriting the relocations for the 'image' variable within the do_bootm function. Out of coincidence the un-initialized memory has a compression type which is the same as the value for the relocation type R_ARM_RELATIVE. Uncompressing Invalid Image ... Unimplemented compression type 23 It should be noted that this is just one way the issue could surface, other cases my not be observed in normal boot flow. Depending on the size of various sections, and location of relocations within __rel_dyn and the compiler/linker the outcome of this bug can differ greatly. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Fixes: 758f29d0 ("ARM: zynq: Support systems with more memory banks") Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
Add two functions for use by board implementations to decode the memory banks of the /memory node so as to populate the global data with ram_size and board info for memory banks. The fdtdec_setup_memory_size() function decodes the first memory bank and sets up the gd->ram_size with the size of the memory bank. This function should be called from the boards dram_init(). The fdtdec_setup_memory_banksize() function decode the memory banks (up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size into the gd->bd->bi_dram array of banks. This function should be called from the boards dram_init_banksize(). Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <monstr@monstr.eu> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Sync with Linux kernel. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
boot.bin file is generated only when SPL is selected. Reflect this depency in Kconfig. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Stop boot process if fpga programming fails. Without this patch boot process continues even if fpga programming failed. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Trivial coding style fix. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
All sata based drivers are bind and corresponding block device is created. Based on this find_scsi_device() is able to get back block device based on scsi_curr_dev pointer. intr_scsi() is commented now but it can be replaced by calling find_scsi_device() and scsi_scan(). scsi_dev_desc[] is commented out but common/scsi.c heavily depends on it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol is reassigned to a block description allocated by uclass. There is only one block description by device now but it doesn't need to be correct when more devices are present. scsi_bind() ensures corresponding block device creation. uclass post_probe (scsi_post_probe()) is doing low level init. SCSI/SATA DM based drivers requires to have 64bit base address as the first entry in platform data structure to setup mmio_base. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Moritz Fischer 提交于
By adding labels to the cpu nodes in the dtsi, a dts that includes it can change the OPPs by referencing the cpu0 through the label. [Based on linux (400b6a0cbef55d1ae32808eaa1ef1c28820bf6ac)] Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: NPhani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
The most of ethernet drivers are using this mdio registration sequence. strcpy(priv->bus->name, "emac"); mdio_register(priv->bus); Where driver can be used only with one MDIO bus because only unique name should be used. Other drivers are using unique device name for MDIO registration to support multiple instances. snprintf(priv->bus->name, sizeof(bus->name), "%s", name); With DM dev->seq is used more even in logs (like random MAC address generation: printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, dev->seq, pdata->enetaddr); ) where eth%d prefix is used. Simplify driver code to register mdio device with dev->seq number to simplify mdio registration and reduce code duplication across all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Marek Vasut 提交于
The EVP_MD_CTX and EVP_CIPHER_CTX are made opaque since 1.1.x , so instead of embedding them directly into struct sb_image_ctx and initializing them using EVP_*_CTX_init(), we use pointers and allocate the crypto contexts using EVP_*_CTX_new(). Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
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由 Marek Vasut 提交于
Shuffle the macros around a little to remove the following warning when building for i.MX28: arch/arm/cpu/arm926ejs/mxs/spl_boot.c:44:26: warning: ‘iomux_boot’ defined but not used [-Wunused-const-variable=] static const iomux_cfg_t iomux_boot[] = { ^~~~~~~~~~ Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Marek Vasut 提交于
Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Marek Vasut 提交于
Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org>
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由 Marek Vasut 提交于
Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 19 12月, 2016 1 次提交
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git://www.denx.de/git/u-boot-imx由 Tom Rini 提交于
Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 17 12月, 2016 21 次提交
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由 Jagan Teki 提交于
Add FEC support for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add FEC node for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add FEC support for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add FEC node for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C support for Engicam i.CoreM6 RQS modules. icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl-rqs> i2c dev 0 Setting bus to 0 icorem6qdl-rqs> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl-rqs> i2c probe Valid chip addresses: 4F icorem6qdl-rqs> i2c md 4F 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 (active 0) 4f: generic_4f, offset len 1, flags 0 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C nodes for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Rename defconfig files for better compatible with respective board names and dts files. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07 +0530) CPU: Freescale i.MX6DL rev1.3 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 DualLite/Solo RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
geam6ul> mtdparts device nand0 <nand>, # parts = 6 0: spl 0x00200000 0x00000000 0 1: uboot 0x00200000 0x00200000 0 2: env 0x00100000 0x00400000 0 3: kernel 0x00400000 0x00500000 0 4: dtb 0x00100000 0x00900000 0 5: rootfs 0x1f600000 0x00a00000 0 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable MTD device, partition and command support. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add NAND support for Engicam GEAM6UL board. Boot Log: -------- U-Boot SPL 2016.11-g537fa5f (Nov 28 2016 - 11:42:28) Trying to boot from NAND NAND : 256 MiB U-Boot 2016.11-g537fa5f (Nov 28 2016 - 11:20:06 +0100) CPU: Freescale i.MX6UL rev1.1 69 MHz (running at 396 MHz) CPU: Automotive temperature grade (-40C to 125C) at 42C Reset cause: WDOG Model: Engicam GEAM6UL DRAM: 128 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 * Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C support for Engicam GEAM6UL module. geam6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 geam6ul> i2c dev 0 Setting bus to 0 geam6ul> i2c dev Current bus is 0 geam6ul> i2c speed 100000 Setting bus speed to 100000 Hz geam6ul> i2c probe Valid chip addresses: 2C geam6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C nodes for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add i.MX6UL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C support for Engicam i.CoreM6 qdl board. icorem6qdl> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl> i2c dev 2 Setting bus to 2 icorem6qdl> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl> i2c probe Valid chip addresses: 2C icorem6qdl> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Jagan Teki 提交于
Some I2C bus devicetree nodes, doesn't require to have gpio pinctrl so replace the dev_info to debug so the print never comes on the console and for bus that uses gpio pinctrl anyway have dev_err. Before: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 0x21a4000, no gpio pinctrl state. After: ------ U-Boot> i2c dev 1 Setting bus to 1 Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Jagan Teki 提交于
Better to print the hex value for bus address instead of decimal, for more readbility on bus addressing. Before: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 35274752, no gpio pinctrl state. After: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 0x21a4000, no gpio pinctrl state. Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NHeiko Schocher <hs@denx.de>
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