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0b4bc1b3
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体验新版 GitCode,发现更多精彩内容 >>
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0b4bc1b3
编写于
12月 16, 2016
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-spi
上级
b5178a1f
9bcb0188
变更
7
隐藏空白更改
内联
并排
Showing
7 changed file
with
95 addition
and
176 deletion
+95
-176
arch/arm/dts/am437x-idk-evm.dts
arch/arm/dts/am437x-idk-evm.dts
+1
-1
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_internal.h
+0
-3
drivers/mtd/spi/spi_flash.c
drivers/mtd/spi/spi_flash.c
+5
-63
drivers/spi/cadence_qspi.c
drivers/spi/cadence_qspi.c
+2
-4
drivers/spi/cadence_qspi.h
drivers/spi/cadence_qspi.h
+1
-2
drivers/spi/cadence_qspi_apb.c
drivers/spi/cadence_qspi_apb.c
+84
-101
drivers/spi/spi-uclass.c
drivers/spi/spi-uclass.c
+2
-2
未找到文件。
arch/arm/dts/am437x-idk-evm.dts
浏览文件 @
0b4bc1b3
...
...
@@ -341,7 +341,7 @@
spi
-
max
-
frequency
=
<
48000000
>;
m25p80
@
0
{
compatible
=
"mx66l51235l"
;
compatible
=
"mx66l51235l"
,
"spi-flash"
;
spi
-
max
-
frequency
=
<
48000000
>;
reg
=
<
0
>;
spi
-
cpol
;
...
...
drivers/mtd/spi/sf_internal.h
浏览文件 @
0b4bc1b3
...
...
@@ -49,7 +49,6 @@ enum spi_nor_option_flags {
#define CMD_WRITE_DISABLE 0x04
#define CMD_WRITE_ENABLE 0x06
#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
...
...
@@ -63,7 +62,6 @@ enum spi_nor_option_flags {
#define CMD_READ_STATUS1 0x35
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
...
...
@@ -78,7 +76,6 @@ enum spi_nor_option_flags {
#define STATUS_QEB_WINSPAN BIT(1)
#define STATUS_QEB_MXIC BIT(6)
#define STATUS_PEC BIT(7)
#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2)
/* Block protect 0 */
#define SR_BP1 BIT(3)
/* Block protect 1 */
#define SR_BP2 BIT(4)
/* Block protect 2 */
...
...
drivers/mtd/spi/spi_flash.c
浏览文件 @
0b4bc1b3
...
...
@@ -112,37 +112,6 @@ static int write_cr(struct spi_flash *flash, u8 wc)
}
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
static
int
read_evcr
(
struct
spi_flash
*
flash
,
u8
*
evcr
)
{
int
ret
;
const
u8
cmd
=
CMD_READ_EVCR
;
ret
=
spi_flash_read_common
(
flash
,
&
cmd
,
1
,
evcr
,
1
);
if
(
ret
<
0
)
{
debug
(
"SF: error reading EVCR
\n
"
);
return
ret
;
}
return
0
;
}
static
int
write_evcr
(
struct
spi_flash
*
flash
,
u8
evcr
)
{
u8
cmd
;
int
ret
;
cmd
=
CMD_WRITE_EVCR
;
ret
=
spi_flash_write_common
(
flash
,
&
cmd
,
1
,
&
evcr
,
1
);
if
(
ret
<
0
)
{
debug
(
"SF: error while writing EVCR register
\n
"
);
return
ret
;
}
return
0
;
}
#endif
#ifdef CONFIG_SPI_FLASH_BAR
static
int
write_bar
(
struct
spi_flash
*
flash
,
u32
offset
)
{
...
...
@@ -894,34 +863,6 @@ static int spansion_quad_enable(struct spi_flash *flash)
}
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
static
int
micron_quad_enable
(
struct
spi_flash
*
flash
)
{
u8
qeb_status
;
int
ret
;
ret
=
read_evcr
(
flash
,
&
qeb_status
);
if
(
ret
<
0
)
return
ret
;
if
(
!
(
qeb_status
&
STATUS_QEB_MICRON
))
return
0
;
ret
=
write_evcr
(
flash
,
qeb_status
&
~
STATUS_QEB_MICRON
);
if
(
ret
<
0
)
return
ret
;
/* read EVCR and check it */
ret
=
read_evcr
(
flash
,
&
qeb_status
);
if
(
!
(
ret
>=
0
&&
!
(
qeb_status
&
STATUS_QEB_MICRON
)))
{
printf
(
"SF: Micron EVCR Quad bit not clear
\n
"
);
return
-
EINVAL
;
}
return
ret
;
}
#endif
static
const
struct
spi_flash_info
*
spi_flash_read_id
(
struct
spi_flash
*
flash
)
{
int
tmp
;
...
...
@@ -962,7 +903,8 @@ static int set_quad_mode(struct spi_flash *flash,
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case
SPI_FLASH_CFI_MFR_STMICRO
:
return
micron_quad_enable
(
flash
);
debug
(
"SF: QEB is volatile for %02x flash
\n
"
,
JEDEC_MFR
(
info
));
return
0
;
#endif
default:
printf
(
"SF: Need set QEB func for %02x flash
\n
"
,
...
...
@@ -985,7 +927,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
return
0
;
}
if
(
flash
->
size
!=
size
)
{
if
(
flash
->
size
>
size
)
{
debug
(
"%s: Memory map must cover entire device
\n
"
,
__func__
);
return
-
1
;
}
...
...
@@ -1000,7 +942,7 @@ int spi_flash_scan(struct spi_flash *flash)
{
struct
spi_slave
*
spi
=
flash
->
spi
;
const
struct
spi_flash_info
*
info
=
NULL
;
int
ret
=
-
1
;
int
ret
;
info
=
spi_flash_read_id
(
flash
);
if
(
IS_ERR_OR_NULL
(
info
))
...
...
@@ -1166,5 +1108,5 @@ int spi_flash_scan(struct spi_flash *flash)
}
#endif
return
ret
;
return
0
;
}
drivers/spi/cadence_qspi.c
浏览文件 @
0b4bc1b3
...
...
@@ -170,14 +170,12 @@ static int cadence_spi_probe(struct udevice *bus)
static
int
cadence_spi_set_mode
(
struct
udevice
*
bus
,
uint
mode
)
{
struct
cadence_spi_priv
*
priv
=
dev_get_priv
(
bus
);
unsigned
int
clk_pol
=
(
mode
&
SPI_CPOL
)
?
1
:
0
;
unsigned
int
clk_pha
=
(
mode
&
SPI_CPHA
)
?
1
:
0
;
/* Disable QSPI */
cadence_qspi_apb_controller_disable
(
priv
->
regbase
);
/* Set SPI mode */
cadence_qspi_apb_set_clk_mode
(
priv
->
regbase
,
clk_pol
,
clk_pha
);
cadence_qspi_apb_set_clk_mode
(
priv
->
regbase
,
mode
);
/* Enable QSPI */
cadence_qspi_apb_controller_enable
(
priv
->
regbase
);
...
...
@@ -298,6 +296,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat
->
regbase
=
(
void
*
)
data
[
0
];
plat
->
ahbbase
=
(
void
*
)
data
[
2
];
plat
->
sram_size
=
fdtdec_get_int
(
blob
,
node
,
"sram-size"
,
128
);
/* All other paramters are embedded in the child node */
subnode
=
fdt_first_subnode
(
blob
,
node
);
...
...
@@ -317,7 +316,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat
->
tsd2d_ns
=
fdtdec_get_int
(
blob
,
subnode
,
"tsd2d-ns"
,
255
);
plat
->
tchsh_ns
=
fdtdec_get_int
(
blob
,
subnode
,
"tchsh-ns"
,
20
);
plat
->
tslch_ns
=
fdtdec_get_int
(
blob
,
subnode
,
"tslch-ns"
,
20
);
plat
->
sram_size
=
fdtdec_get_int
(
blob
,
node
,
"sram-size"
,
128
);
debug
(
"%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d
\n
"
,
__func__
,
plat
->
regbase
,
plat
->
ahbbase
,
plat
->
max_hz
,
...
...
drivers/spi/cadence_qspi.h
浏览文件 @
0b4bc1b3
...
...
@@ -63,8 +63,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
void
cadence_qspi_apb_chipselect
(
void
*
reg_base
,
unsigned
int
chip_select
,
unsigned
int
decoder_enable
);
void
cadence_qspi_apb_set_clk_mode
(
void
*
reg_base_addr
,
unsigned
int
clk_pol
,
unsigned
int
clk_pha
);
void
cadence_qspi_apb_set_clk_mode
(
void
*
reg_base
,
uint
mode
);
void
cadence_qspi_apb_config_baudrate_div
(
void
*
reg_base
,
unsigned
int
ref_clk_hz
,
unsigned
int
sclk_hz
);
void
cadence_qspi_apb_delay
(
void
*
reg_base
,
...
...
drivers/spi/cadence_qspi_apb.c
浏览文件 @
0b4bc1b3
...
...
@@ -32,37 +32,37 @@
#include <spi.h>
#include "cadence_qspi.h"
#define CQSPI_REG_POLL_US
(1)
/* 1us */
#define CQSPI_REG_RETRY
(10000)
#define CQSPI_POLL_IDLE_RETRY
(3)
#define CQSPI_REG_POLL_US
1
/* 1us */
#define CQSPI_REG_RETRY
10000
#define CQSPI_POLL_IDLE_RETRY
3
#define CQSPI_FIFO_WIDTH
(4)
#define CQSPI_FIFO_WIDTH
4
#define CQSPI_REG_SRAM_THRESHOLD_WORDS
(50)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS
50
/* Transfer mode */
#define CQSPI_INST_TYPE_SINGLE
(0)
#define CQSPI_INST_TYPE_DUAL
(1)
#define CQSPI_INST_TYPE_QUAD
(2)
#define CQSPI_INST_TYPE_SINGLE
0
#define CQSPI_INST_TYPE_DUAL
1
#define CQSPI_INST_TYPE_QUAD
2
#define CQSPI_STIG_DATA_LEN_MAX (8)
#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
#define CQSPI_DUMMY_BYTES_MAX (4)
#define CQSPI_STIG_DATA_LEN_MAX 8
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
#define CQSPI_REG_SRAM_FILL_THRESHOLD \
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/
#define CQSPI_REG_CONFIG 0x00
#define CQSPI_REG_CONFIG_
CLK_POL_LSB 1
#define CQSPI_REG_CONFIG_CLK_P
HA_LSB 2
#define CQSPI_REG_CONFIG_
ENABLE_MASK BIT(0
)
#define CQSPI_REG_CONFIG_DIRECT
_MASK
BIT(7)
#define CQSPI_REG_CONFIG_DECODE
_MASK
BIT(9)
#define CQSPI_REG_CONFIG_XIP_IMM
_MASK
BIT(18)
#define CQSPI_REG_CONFIG_
ENABLE BIT(0)
#define CQSPI_REG_CONFIG_CLK_P
OL BIT(1)
#define CQSPI_REG_CONFIG_
CLK_PHA BIT(2
)
#define CQSPI_REG_CONFIG_DIRECT
BIT(7)
#define CQSPI_REG_CONFIG_DECODE
BIT(9)
#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31
...
...
@@ -94,10 +94,10 @@
#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
#define CQSPI_RE
ADLCAPTURE
0x10
#define CQSPI_RE
ADLCAPTURE_BYPASS_LSB 0
#define CQSPI_RE
ADLCAPTURE_DELAY_LSB
1
#define CQSPI_RE
ADLCAPTURE_DELAY_MASK
0xF
#define CQSPI_RE
G_RD_DATA_CAPTURE
0x10
#define CQSPI_RE
G_RD_DATA_CAPTURE_BYPASS BIT(0)
#define CQSPI_RE
G_RD_DATA_CAPTURE_DELAY_LSB
1
#define CQSPI_RE
G_RD_DATA_CAPTURE_DELAY_MASK
0xF
#define CQSPI_REG_SIZE 0x14
#define CQSPI_REG_SIZE_ADDRESS_LSB 0
...
...
@@ -123,18 +123,18 @@
#define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60
#define CQSPI_REG_INDIRECTRD_START
_MASK
BIT(0)
#define CQSPI_REG_INDIRECTRD_CANCEL
_MASK
BIT(1)
#define CQSPI_REG_INDIRECTRD_INPROGRESS
_MASK
BIT(2)
#define CQSPI_REG_INDIRECTRD_DONE
_MASK
BIT(5)
#define CQSPI_REG_INDIRECTRD_START BIT(0)
#define CQSPI_REG_INDIRECTRD_CANCEL
BIT(1)
#define CQSPI_REG_INDIRECTRD_INPROGRESS
BIT(2)
#define CQSPI_REG_INDIRECTRD_DONE BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90
#define CQSPI_REG_CMDCTRL_EXECUTE
_MASK
BIT(0)
#define CQSPI_REG_CMDCTRL_INPROGRESS
_MASK
BIT(1)
#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
#define CQSPI_REG_CMDCTRL_INPROGRESS
BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
...
...
@@ -150,10 +150,10 @@
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
#define CQSPI_REG_INDIRECTWR 0x70
#define CQSPI_REG_INDIRECTWR_START
_MASK
BIT(0)
#define CQSPI_REG_INDIRECTWR_CANCEL
_MASK
BIT(1)
#define CQSPI_REG_INDIRECTWR_INPROGRESS
_MASK
BIT(2)
#define CQSPI_REG_INDIRECTWR_DONE
_MASK
BIT(5)
#define CQSPI_REG_INDIRECTWR_START BIT(0)
#define CQSPI_REG_INDIRECTWR_CANCEL
BIT(1)
#define CQSPI_REG_INDIRECTWR_INPROGRESS
BIT(2)
#define CQSPI_REG_INDIRECTWR_DONE BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
...
...
@@ -169,9 +169,6 @@
((readl(base + CQSPI_REG_CONFIG) >> \
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
...
...
@@ -197,18 +194,16 @@ void cadence_qspi_apb_controller_enable(void *reg_base)
{
unsigned
int
reg
;
reg
=
readl
(
reg_base
+
CQSPI_REG_CONFIG
);
reg
|=
CQSPI_REG_CONFIG_ENABLE
_MASK
;
reg
|=
CQSPI_REG_CONFIG_ENABLE
;
writel
(
reg
,
reg_base
+
CQSPI_REG_CONFIG
);
return
;
}
void
cadence_qspi_apb_controller_disable
(
void
*
reg_base
)
{
unsigned
int
reg
;
reg
=
readl
(
reg_base
+
CQSPI_REG_CONFIG
);
reg
&=
~
CQSPI_REG_CONFIG_ENABLE
_MASK
;
reg
&=
~
CQSPI_REG_CONFIG_ENABLE
;
writel
(
reg
,
reg_base
+
CQSPI_REG_CONFIG
);
return
;
}
/* Return 1 if idle, otherwise return 0 (busy). */
...
...
@@ -244,23 +239,22 @@ void cadence_qspi_apb_readdata_capture(void *reg_base,
unsigned
int
reg
;
cadence_qspi_apb_controller_disable
(
reg_base
);
reg
=
readl
(
reg_base
+
CQSPI_RE
ADL
CAPTURE
);
reg
=
readl
(
reg_base
+
CQSPI_RE
G_RD_DATA_
CAPTURE
);
if
(
bypass
)
reg
|=
(
1
<<
CQSPI_READLCAPTURE_BYPASS_LSB
)
;
reg
|=
CQSPI_REG_RD_DATA_CAPTURE_BYPASS
;
else
reg
&=
~
(
1
<<
CQSPI_READLCAPTURE_BYPASS_LSB
)
;
reg
&=
~
CQSPI_REG_RD_DATA_CAPTURE_BYPASS
;
reg
&=
~
(
CQSPI_RE
ADL
CAPTURE_DELAY_MASK
<<
CQSPI_RE
ADL
CAPTURE_DELAY_LSB
);
reg
&=
~
(
CQSPI_RE
G_RD_DATA_
CAPTURE_DELAY_MASK
<<
CQSPI_RE
G_RD_DATA_
CAPTURE_DELAY_LSB
);
reg
|=
(
(
delay
&
CQSPI_READL
CAPTURE_DELAY_MASK
)
<<
CQSPI_RE
ADLCAPTURE_DELAY_LSB
)
;
reg
|=
(
delay
&
CQSPI_REG_RD_DATA_
CAPTURE_DELAY_MASK
)
<<
CQSPI_RE
G_RD_DATA_CAPTURE_DELAY_LSB
;
writel
(
reg
,
reg_base
+
CQSPI_RE
ADL
CAPTURE
);
writel
(
reg
,
reg_base
+
CQSPI_RE
G_RD_DATA_
CAPTURE
);
cadence_qspi_apb_controller_enable
(
reg_base
);
return
;
}
void
cadence_qspi_apb_config_baudrate_div
(
void
*
reg_base
,
...
...
@@ -273,54 +267,42 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base,
reg
=
readl
(
reg_base
+
CQSPI_REG_CONFIG
);
reg
&=
~
(
CQSPI_REG_CONFIG_BAUD_MASK
<<
CQSPI_REG_CONFIG_BAUD_LSB
);
div
=
ref_clk_hz
/
sclk_hz
;
if
(
div
>
32
)
div
=
32
;
/* Check if even number. */
if
((
div
&
1
))
{
div
=
(
div
/
2
);
}
else
{
if
(
ref_clk_hz
%
sclk_hz
)
/* ensure generated SCLK doesn't exceed user
specified sclk_hz */
div
=
(
div
/
2
);
else
div
=
(
div
/
2
)
-
1
;
}
debug
(
"%s: ref_clk %dHz sclk %dHz Div 0x%x
\n
"
,
__func__
,
ref_clk_hz
,
sclk_hz
,
div
);
/*
* The baud_div field in the config reg is 4 bits, and the ref clock is
* divided by 2 * (baud_div + 1). Round up the divider to ensure the
* SPI clock rate is less than or equal to the requested clock rate.
*/
div
=
DIV_ROUND_UP
(
ref_clk_hz
,
sclk_hz
*
2
)
-
1
;
/* ensure the baud rate doesn't exceed the max value */
if
(
div
>
CQSPI_REG_CONFIG_BAUD_MASK
)
div
=
CQSPI_REG_CONFIG_BAUD_MASK
;
debug
(
"%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz
\n
"
,
__func__
,
ref_clk_hz
,
sclk_hz
,
div
,
ref_clk_hz
/
(
2
*
(
div
+
1
)));
reg
|=
(
div
<<
CQSPI_REG_CONFIG_BAUD_LSB
);
writel
(
reg
,
reg_base
+
CQSPI_REG_CONFIG
);
cadence_qspi_apb_controller_enable
(
reg_base
);
return
;
}
void
cadence_qspi_apb_set_clk_mode
(
void
*
reg_base
,
unsigned
int
clk_pol
,
unsigned
int
clk_pha
)
void
cadence_qspi_apb_set_clk_mode
(
void
*
reg_base
,
uint
mode
)
{
unsigned
int
reg
;
cadence_qspi_apb_controller_disable
(
reg_base
);
reg
=
readl
(
reg_base
+
CQSPI_REG_CONFIG
);
reg
&=
~
(
1
<<
(
CQSPI_REG_CONFIG_CLK_POL_LSB
|
CQSPI_REG_CONFIG_CLK_PHA_LSB
));
reg
&=
~
(
CQSPI_REG_CONFIG_CLK_POL
|
CQSPI_REG_CONFIG_CLK_PHA
);
reg
|=
((
clk_pol
&
0x1
)
<<
CQSPI_REG_CONFIG_CLK_POL_LSB
);
reg
|=
((
clk_pha
&
0x1
)
<<
CQSPI_REG_CONFIG_CLK_PHA_LSB
);
if
(
mode
&
SPI_CPOL
)
reg
|=
CQSPI_REG_CONFIG_CLK_POL
;
if
(
mode
&
SPI_CPHA
)
reg
|=
CQSPI_REG_CONFIG_CLK_PHA
;
writel
(
reg
,
reg_base
+
CQSPI_REG_CONFIG
);
cadence_qspi_apb_controller_enable
(
reg_base
);
return
;
}
void
cadence_qspi_apb_chipselect
(
void
*
reg_base
,
...
...
@@ -336,9 +318,9 @@ void cadence_qspi_apb_chipselect(void *reg_base,
reg
=
readl
(
reg_base
+
CQSPI_REG_CONFIG
);
/* docoder */
if
(
decoder_enable
)
{
reg
|=
CQSPI_REG_CONFIG_DECODE
_MASK
;
reg
|=
CQSPI_REG_CONFIG_DECODE
;
}
else
{
reg
&=
~
CQSPI_REG_CONFIG_DECODE
_MASK
;
reg
&=
~
CQSPI_REG_CONFIG_DECODE
;
/* Convert CS if without decoder.
* CS0 to 4b'1110
* CS1 to 4b'1101
...
...
@@ -355,7 +337,6 @@ void cadence_qspi_apb_chipselect(void *reg_base,
writel
(
reg
,
reg_base
+
CQSPI_REG_CONFIG
);
cadence_qspi_apb_controller_enable
(
reg_base
);
return
;
}
void
cadence_qspi_apb_delay
(
void
*
reg_base
,
...
...
@@ -371,16 +352,20 @@ void cadence_qspi_apb_delay(void *reg_base,
cadence_qspi_apb_controller_disable
(
reg_base
);
/* Convert to ns. */
ref_clk_ns
=
(
1000000000
)
/
ref_clk
;
ref_clk_ns
=
DIV_ROUND_UP
(
1000000000
,
ref_clk
)
;
/* Convert to ns. */
sclk_ns
=
(
1000000000
)
/
sclk_hz
;
/* Plus 1 to round up 1 clock cycle. */
tshsl
=
CQSPI_CAL_DELAY
(
tshsl_ns
,
ref_clk_ns
,
sclk_ns
)
+
1
;
tchsh
=
CQSPI_CAL_DELAY
(
tchsh_ns
,
ref_clk_ns
,
sclk_ns
)
+
1
;
tslch
=
CQSPI_CAL_DELAY
(
tslch_ns
,
ref_clk_ns
,
sclk_ns
)
+
1
;
tsd2d
=
CQSPI_CAL_DELAY
(
tsd2d_ns
,
ref_clk_ns
,
sclk_ns
)
+
1
;
sclk_ns
=
DIV_ROUND_UP
(
1000000000
,
sclk_hz
);
/* The controller adds additional delay to that programmed in the reg */
if
(
tshsl_ns
>=
sclk_ns
+
ref_clk_ns
)
tshsl_ns
-=
sclk_ns
+
ref_clk_ns
;
if
(
tchsh_ns
>=
sclk_ns
+
3
*
ref_clk_ns
)
tchsh_ns
-=
sclk_ns
+
3
*
ref_clk_ns
;
tshsl
=
DIV_ROUND_UP
(
tshsl_ns
,
ref_clk_ns
);
tchsh
=
DIV_ROUND_UP
(
tchsh_ns
,
ref_clk_ns
);
tslch
=
DIV_ROUND_UP
(
tslch_ns
,
ref_clk_ns
);
tsd2d
=
DIV_ROUND_UP
(
tsd2d_ns
,
ref_clk_ns
);
reg
=
((
tshsl
&
CQSPI_REG_DELAY_TSHSL_MASK
)
<<
CQSPI_REG_DELAY_TSHSL_LSB
);
...
...
@@ -393,7 +378,6 @@ void cadence_qspi_apb_delay(void *reg_base,
writel
(
reg
,
reg_base
+
CQSPI_REG_DELAY
);
cadence_qspi_apb_controller_enable
(
reg_base
);
return
;
}
void
cadence_qspi_apb_controller_init
(
struct
cadence_spi_platdata
*
plat
)
...
...
@@ -421,7 +405,6 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
writel
(
0
,
plat
->
regbase
+
CQSPI_REG_IRQMASK
);
cadence_qspi_apb_controller_enable
(
plat
->
regbase
);
return
;
}
static
int
cadence_qspi_apb_exec_flash_cmd
(
void
*
reg_base
,
...
...
@@ -432,12 +415,12 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
/* Write the CMDCTRL without start execution. */
writel
(
reg
,
reg_base
+
CQSPI_REG_CMDCTRL
);
/* Start execute */
reg
|=
CQSPI_REG_CMDCTRL_EXECUTE
_MASK
;
reg
|=
CQSPI_REG_CMDCTRL_EXECUTE
;
writel
(
reg
,
reg_base
+
CQSPI_REG_CMDCTRL
);
while
(
retry
--
)
{
reg
=
readl
(
reg_base
+
CQSPI_REG_CMDCTRL
);
if
((
reg
&
CQSPI_REG_CMDCTRL_INPROGRESS
_MASK
)
==
0
)
if
((
reg
&
CQSPI_REG_CMDCTRL_INPROGRESS
)
==
0
)
break
;
udelay
(
1
);
}
...
...
@@ -655,7 +638,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
writel
(
n_rx
,
plat
->
regbase
+
CQSPI_REG_INDIRECTRDBYTES
);
/* Start the indirect read transfer */
writel
(
CQSPI_REG_INDIRECTRD_START
_MASK
,
writel
(
CQSPI_REG_INDIRECTRD_START
,
plat
->
regbase
+
CQSPI_REG_INDIRECTRD
);
while
(
remaining
>
0
)
{
...
...
@@ -684,21 +667,21 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
/* Check indirect done status */
ret
=
wait_for_bit
(
"QSPI"
,
plat
->
regbase
+
CQSPI_REG_INDIRECTRD
,
CQSPI_REG_INDIRECTRD_DONE
_MASK
,
1
,
10
,
0
);
CQSPI_REG_INDIRECTRD_DONE
,
1
,
10
,
0
);
if
(
ret
)
{
printf
(
"Indirect read completion error (%i)
\n
"
,
ret
);
goto
failrd
;
}
/* Clear indirect completion status */
writel
(
CQSPI_REG_INDIRECTRD_DONE
_MASK
,
writel
(
CQSPI_REG_INDIRECTRD_DONE
,
plat
->
regbase
+
CQSPI_REG_INDIRECTRD
);
return
0
;
failrd:
/* Cancel the indirect read */
writel
(
CQSPI_REG_INDIRECTRD_CANCEL
_MASK
,
writel
(
CQSPI_REG_INDIRECTRD_CANCEL
,
plat
->
regbase
+
CQSPI_REG_INDIRECTRD
);
return
ret
;
}
...
...
@@ -746,7 +729,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
writel
(
n_tx
,
plat
->
regbase
+
CQSPI_REG_INDIRECTWRBYTES
);
/* Start the indirect write transfer */
writel
(
CQSPI_REG_INDIRECTWR_START
_MASK
,
writel
(
CQSPI_REG_INDIRECTWR_START
,
plat
->
regbase
+
CQSPI_REG_INDIRECTWR
);
while
(
remaining
>
0
)
{
...
...
@@ -771,20 +754,20 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
/* Check indirect done status */
ret
=
wait_for_bit
(
"QSPI"
,
plat
->
regbase
+
CQSPI_REG_INDIRECTWR
,
CQSPI_REG_INDIRECTWR_DONE
_MASK
,
1
,
10
,
0
);
CQSPI_REG_INDIRECTWR_DONE
,
1
,
10
,
0
);
if
(
ret
)
{
printf
(
"Indirect write completion error (%i)
\n
"
,
ret
);
goto
failwr
;
}
/* Clear indirect completion status */
writel
(
CQSPI_REG_INDIRECTWR_DONE
_MASK
,
writel
(
CQSPI_REG_INDIRECTWR_DONE
,
plat
->
regbase
+
CQSPI_REG_INDIRECTWR
);
return
0
;
failwr:
/* Cancel the indirect write */
writel
(
CQSPI_REG_INDIRECTWR_CANCEL
_MASK
,
writel
(
CQSPI_REG_INDIRECTWR_CANCEL
,
plat
->
regbase
+
CQSPI_REG_INDIRECTWR
);
return
ret
;
}
...
...
@@ -795,9 +778,9 @@ void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
/* enter XiP mode immediately and enable direct mode */
reg
=
readl
(
reg_base
+
CQSPI_REG_CONFIG
);
reg
|=
CQSPI_REG_CONFIG_ENABLE
_MASK
;
reg
|=
CQSPI_REG_CONFIG_DIRECT
_MASK
;
reg
|=
CQSPI_REG_CONFIG_XIP_IMM
_MASK
;
reg
|=
CQSPI_REG_CONFIG_ENABLE
;
reg
|=
CQSPI_REG_CONFIG_DIRECT
;
reg
|=
CQSPI_REG_CONFIG_XIP_IMM
;
writel
(
reg
,
reg_base
+
CQSPI_REG_CONFIG
);
/* keep the XiP mode */
...
...
drivers/spi/spi-uclass.c
浏览文件 @
0b4bc1b3
...
...
@@ -418,7 +418,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode
|=
SPI_TX_QUAD
;
break
;
default:
error
(
"spi-tx-bus-width %d not supported
\n
"
,
value
);
warn_non_spl
(
"spi-tx-bus-width %d not supported
\n
"
,
value
);
break
;
}
...
...
@@ -433,7 +433,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode
|=
SPI_RX_QUAD
;
break
;
default:
error
(
"spi-rx-bus-width %d not supported
\n
"
,
value
);
warn_non_spl
(
"spi-rx-bus-width %d not supported
\n
"
,
value
);
break
;
}
...
...
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