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  1. 10 7月, 2021 12 次提交
    • A
      mmc: sunxi: Fix MMC clock parent selection · 937ee31e
      由 Andre Przywara 提交于 
      Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.

Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.

Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      937ee31e
    • A
      mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT · ca496baf
      由 Andre Przywara 提交于 
      When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about
pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which
are always below 1GB on all Allwinner SoCs, so there is no problem with
anything having more than 32 bits.

Add the proper casts to make it compile cleanly.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
      ca496baf
    • A
      mmc: sunxi: Avoid #ifdefs in delay and width setup · f4826fb1
      由 Andre Przywara 提交于 
      The delay and bus-width setup are slightly different across the
Allwinner SoC generations, and we covered this so far with some
preprocessor conditionals.

Use the more readable IS_ENABLE() instead.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
      f4826fb1
    • A
      sunxi: H616: Enable full 4GB of DRAM · b8747854
      由 Andre Przywara 提交于 
      The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.

Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.

As not all devices are actually capable of dealing with more than 32
bits (the DMA in the EMAC for instance), we also limit U-Boot's own
DRAM usage to 4GB on the way.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      b8747854
    • A
      sunxi: board: Add H616 MMC2 pins · 212224ed
      由 Andre Przywara 提交于 
      We hardcode the pinctrl setting for the MMC controllers in boards.c,
since we need them also in the SPL, where there is no DT yet.

Add the respective setting for the H616 SoC, to enable eMMC on boards
with this SoC as well.
Also to make diagnosing this problem easier, print a warning if a board
tries to setup MMC2 pins without a respective SoC setting being defined.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec at siol.net>
      212224ed
    • Y
      sunxi: h3: Add initial ZeroPi support · 2527b24f
      由 Yu-Tung Chang 提交于 
      ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.

ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by: NYu-Tung Chang <mtwget@gmail.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      2527b24f
    • J
      configs: OrangePi PC2: Update defaults · 8e6eed57
      由 Jernej Skrabec 提交于 
      OrangePi PC2 board has DRAM with ODT, so enable it.
H5 SoC is also connected to voltage regulator. It's default value is
reasonable at reset, but might be too low when rebooting with a lower
voltage programmed. In order to avoid instability, enable driver for it
and set it to appropriate voltage.
Signed-off-by: NJernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: NAndre Przywara <andre.przywara@arm.com>
[Andre: remove original ZQ value change, adjust commit message]
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      8e6eed57
    • A
      sunxi: clock: H6/H616: Fix PLL clock factor encodings · f9d13247
      由 Andre Przywara 提交于 
      Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.

This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000

Also the CPU frequency (PLL1) was a tad too high before.

For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NJernej Skrabec <jernej.skrabec@gmail.com>
      f9d13247
    • P
      phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB · 0d5824cb
      由 Paul Kocialkowski 提交于 
      Recent Allwinner platforms (starting with the H3) only use the MUSB
controller for peripheral mode and use HCI for host mode. As a result,
extra steps need to be taken to properly route USB signals to one or
the other. More precisely, the following is required:
* Routing the pins to either HCI/MUSB (controlled by PHY);
* Enabling USB PHY passby in HCI mode (controlled by PMU).

The current code will enable passby for each PHY and reroute PHY0 to
MUSB, which is inconsistent and results in broken USB peripheral support.

Passby on PHY0 must only be enabled when we want to use HCI. Since
host/device mode detection is not available from the PHY code and
because U-Boot does not support changing the mode dynamically anyway,
we can just mux the controller to MUSB if it is enabled and mux it to
HCI otherwise.

This fixes USB peripheral support for platforms with PHY0 dual-route,
especially H3/H5 and V3s.
Signed-off-by: NPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      0d5824cb
    • A
      arm: dts: sunxi: h3: Update DT files · 8fcf1fa2
      由 Andre Przywara 提交于 
      Update the H3 DT files from the Linux 5.12 release.

The changes update some boards, and don't affect U-Boot, but fix Gigabit
Ethernet when this DT is passed on to the Linux kernel.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      8fcf1fa2
    • A
      arm: dts: sunxi: h5: Update DT files · 58f68611
      由 Andre Przywara 提交于 
      Update the H5 DT files from the Linux 5.12 release.

The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
this DT is passed on to the Linux kernel. It also introduces DVFS.

This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
that are of no concern to U-Boot.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      58f68611
    • A
      arm: dts: sunxi: h6: Update DT files · 127e57c6
      由 Andre Przywara 提交于 
      Update the H6 DT files from the Linux 5.12 release.

The changes are minimal (many LED node renames), but also help to enable
USB port 0 in U-Boot (later), enable the RSB device (not yet used in
U-Boot), and also introduce an MMC frequency limit.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      127e57c6
  3. 08 7月, 2021 28 次提交