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提交 bfb5bfa3 编写于 作者: T Tom Rini
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Merge branch '2021-07-07-remove-non-migrated-platforms' 

- Remove a large number of platforms that did not migrate to DM_PCI or
  DM_USB by 2 years past the migration deadline and do not have a
  migration imminent.
上级 7e58a3a1 123dc510
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Showing with 76 addition and 38143 deletion
.azure-pipelines.yml
浏览文件 @ bfb5bfa3
......@@ -417,7 +417,7 @@ jobs:
t208xrdb_corenet_ds:
BUILDMAN: "t208xrdb corenet_ds"
fsl_ppc:
BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
t102x:
BUILDMAN: "t102*"
p1_p2_rdb_pc:
......
MAINTAINERS
浏览文件 @ bfb5bfa3
......@@ -1002,12 +1002,6 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
RISC-V
M: Rick Chen <rick@andestech.com>
M: Leo <ycliang@andestech.com>
......
Makefile
浏览文件 @ bfb5bfa3
......@@ -1561,22 +1561,11 @@ u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin
u-boot.sb: u-boot.bin spl/u-boot-spl.bin
$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
# bootloader can check its integrity. Padding needs to be done to the
# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
# The resulting image containing both U-Boot images is called u-boot.spr
MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \
-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER
spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0xff
u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
ifneq ($(CONFIG_ARCH_SOCFPGA),)
quiet_cmd_gensplx4 = GENSPLX4 $@
cmd_gensplx4 = $(OBJCOPY) -I binary -O binary --gap-fill=0x0 \
......
README
浏览文件 @ bfb5bfa3
......@@ -423,8 +423,7 @@ The following options need to be configured:
CONFIG_SYS_FSL_DDR
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
SoCs.
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
......@@ -630,10 +629,6 @@ The following options need to be configured:
controller register space
- Serial Ports:
CONFIG_PL010_SERIAL
Define this if you want support for Amba PrimeCell PL010 UARTs.
CONFIG_PL011_SERIAL
Define this if you want support for Amba PrimeCell PL011 UARTs.
......
arch/arm/Kconfig
浏览文件 @ bfb5bfa3
......@@ -525,22 +525,11 @@ config ARCH_AT91
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
select GPIO_EXTRA_HEADER
select PL010_SERIAL
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
config TARGET_GPLUGD
bool "Support gplugd"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
......@@ -577,38 +566,6 @@ config ARCH_ORION5X
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
config TARGET_SPEAR300
bool "Support spear300"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
config TARGET_SPEAR310
bool "Support spear310"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
config TARGET_SPEAR320
bool "Support spear320"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
config TARGET_SPEAR600
bool "Support spear600"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
config TARGET_STV0991
bool "Support stv0991"
select CPU_V7A
......@@ -622,14 +579,6 @@ config TARGET_STV0991
select SPI_FLASH
imply CMD_DM
config TARGET_X600
bool "Support x600"
select BOARD_LATE_INIT
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config TARGET_FLEA3
bool "Support flea3"
select CPU_ARM1136
......@@ -2096,7 +2045,6 @@ source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
source "board/armltd/vexpress64/Kconfig"
......@@ -2106,7 +2054,6 @@ source "board/broadcom/bcm968360bg/Kconfig"
source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
......@@ -2135,11 +2082,6 @@ source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
......
arch/arm/cpu/arm920t/start.S
浏览文件 @ bfb5bfa3
......@@ -35,7 +35,7 @@ reset:
orr r0, r0, #0xd3
msr cpsr, r0
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
#if defined(CONFIG_AT91RM9200DK)
/*
* relocate exception table
*/
......
arch/arm/cpu/arm926ejs/spear/Makefile 已删除 100644 → 0
浏览文件 @ 7e58a3a1
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := cpu.o \
reset.o \
timer.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_SPEAR600) += spear600.o
obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
else
obj-y += spr_misc.o spr_lowlevel_init.o
endif
extra-$(CONFIG_SPL_BUILD) := start.o
arch/arm/cpu/arm926ejs/spear/cpu.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_misc.h>
int arch_cpu_init(void)
{
struct misc_regs *const misc_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 periph1_clken, periph_clk_cfg;
periph1_clken = readl(&misc_p->periph1_clken);
#if defined(CONFIG_SPEAR3XX)
periph1_clken |= MISC_GPT2ENB;
#elif defined(CONFIG_SPEAR600)
periph1_clken |= MISC_GPT3ENB;
#endif
#if defined(CONFIG_PL011_SERIAL)
periph1_clken |= MISC_UART0ENB;
periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
periph_clk_cfg |= CONFIG_SPEAR_UART48M;
writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
#endif
#if defined(CONFIG_ETH_DESIGNWARE)
periph1_clken |= MISC_ETHENB;
#endif
#if defined(CONFIG_DW_UDC)
periph1_clken |= MISC_USBDENB;
#endif
#if defined(CONFIG_SYS_I2C_DW)
periph1_clken |= MISC_I2CENB;
#endif
#if defined(CONFIG_ST_SMI)
periph1_clken |= MISC_SMIENB;
#endif
#if defined(CONFIG_NAND_FSMC)
periph1_clken |= MISC_FSMCENB;
#endif
#if defined(CONFIG_USB_EHCI_SPEAR)
periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
#endif
#if defined(CONFIG_SPEAR_GPIO)
periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
#endif
#if defined(CONFIG_PL022_SPI)
periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
#endif
writel(periph1_clken, &misc_p->periph1_clken);
return 0;
}
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
#ifdef CONFIG_SPEAR300
printf("CPU: SPEAr300\n");
#elif defined(CONFIG_SPEAR310)
printf("CPU: SPEAr310\n");
#elif defined(CONFIG_SPEAR320)
printf("CPU: SPEAr320\n");
#elif defined(CONFIG_SPEAR600)
printf("CPU: SPEAr600\n");
#else
#error CPU not supported in spear platform
#endif
return 0;
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
if (argc != 2)
goto usage;
if (strncmp(argv[1], "hw", 2) == 0) {
/* 1-bit HW ECC */
printf("Switching to 1-bit HW ECC\n");
fsmc_nand_switch_ecc(1);
} else if (strncmp(argv[1], "bch4", 2) == 0) {
/* 4-bit SW ECC BCH4 */
printf("Switching to 4-bit SW ECC (BCH4)\n");
fsmc_nand_switch_ecc(4);
} else {
goto usage;
}
return 0;
usage:
printf("Usage: nandecc %s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
nandecc, 2, 0, do_switch_ecc,
"switch NAND ECC calculation algorithm",
"hw|bch4 - Switch between NAND hardware 1-bit HW and"
" 4-bit SW BCH\n"
);
#endif
arch/arm/cpu/arm926ejs/spear/reset.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_syscntl.h>
#include <linux/delay.h>
void reset_cpu(void)
{
struct syscntl_regs *syscntl_regs_p =
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
printf("System is going to reboot ...\n");
/*
* This 1 second delay will allow the above message
* to be printed before reset
*/
udelay((1000 * 1000));
/* Going into slow mode before resetting SOC */
writel(0x02, &syscntl_regs_p->scctrl);
/*
* Writing any value to the system status register will
* reset the SoC
*/
writel(0x00, &syscntl_regs_p->scsysstat);
/* system will restart */
while (1)
;
}
arch/arm/cpu/arm926ejs/spear/spear600.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*/
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_defs.h>
void spear_late_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
writel(0x80000007, &misc_p->arb_icm_ml1);
writel(0x80000007, &misc_p->arb_icm_ml2);
writel(0x80000007, &misc_p->arb_icm_ml3);
writel(0x80000007, &misc_p->arb_icm_ml4);
writel(0x80000007, &misc_p->arb_icm_ml5);
writel(0x80000007, &misc_p->arb_icm_ml6);
writel(0x80000007, &misc_p->arb_icm_ml7);
writel(0x80000007, &misc_p->arb_icm_ml8);
writel(0x80000007, &misc_p->arb_icm_ml9);
}
static void sel_1v8(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 ddr1v8, ddr2v5;
ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
ddr2v5 &= 0x8080ffc0;
ddr2v5 |= 0x78000003;
writel(ddr2v5, &misc_p->ddr_2v5_compensation);
ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
ddr1v8 &= 0x8080ffc0;
ddr1v8 |= 0x78000010;
writel(ddr1v8, &misc_p->ddr_1v8_compensation);
while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
;
}
static void sel_2v5(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 ddr1v8, ddr2v5;
ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
ddr1v8 &= 0x8080ffc0;
ddr1v8 |= 0x78000003;
writel(ddr1v8, &misc_p->ddr_1v8_compensation);
ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
ddr2v5 &= 0x8080ffc0;
ddr2v5 |= 0x78000010;
writel(ddr2v5, &misc_p->ddr_2v5_compensation);
while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
;
}
/*
* plat_ddr_init:
*/
void plat_ddr_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 ddrpad;
u32 core3v3, ddr1v8, ddr2v5;
/* DDR pad register configurations */
ddrpad = readl(&misc_p->ddr_pad);
ddrpad &= ~DDR_PAD_CNF_MSK;
#if (CONFIG_DDR_HCLK)
ddrpad |= 0xEAAB;
#elif (CONFIG_DDR_2HCLK)
ddrpad |= 0xEAAD;
#elif (CONFIG_DDR_PLL2)
ddrpad |= 0xEAAD;
#endif
writel(ddrpad, &misc_p->ddr_pad);
/* Compensation register configurations */
core3v3 = readl(&misc_p->core_3v3_compensation);
core3v3 &= 0x8080ffe0;
core3v3 |= 0x78000002;
writel(core3v3, &misc_p->core_3v3_compensation);
ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
ddr1v8 &= 0x8080ffc0;
ddr1v8 |= 0x78000004;
writel(ddr1v8, &misc_p->ddr_1v8_compensation);
ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
ddr2v5 &= 0x8080ffc0;
ddr2v5 |= 0x78000004;
writel(ddr2v5, &misc_p->ddr_2v5_compensation);
if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
/* Software memory configuration */
if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
sel_1v8();
else
sel_2v5();
} else {
/* Hardware memory configuration */
if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
sel_1v8();
else
sel_2v5();
}
}
/*
* xxx_boot_selected:
*
* return true if the particular booting option is selected
* return false otherwise
*/
static u32 read_bootstrap(void)
{
return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
& CONFIG_SPEAR_BOOTSTRAPMASK;
}
int snor_boot_selected(void)
{
u32 bootstrap = read_bootstrap();
if (SNOR_BOOT_SUPPORTED) {
/* Check whether SNOR boot is selected */
if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
CONFIG_SPEAR_ONLYSNORBOOT)
return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
return true;
}
return false;
}
int nand_boot_selected(void)
{
u32 bootstrap = read_bootstrap();
if (NAND_BOOT_SUPPORTED) {
/* Check whether NAND boot is selected */
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
return true;
}
return false;
}
int pnor_boot_selected(void)
{
/* Parallel NOR boot is not selected in any SPEAr600 revision */
return false;
}
int usb_boot_selected(void)
{
u32 bootstrap = read_bootstrap();
if (USB_BOOT_SUPPORTED) {
/* Check whether USB boot is selected */
if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
return true;
}
return false;
}
int tftp_boot_selected(void)
{
/* TFTP boot is not selected in any SPEAr600 revision */
return false;
}
int uart_boot_selected(void)
{
/* UART boot is not selected in any SPEAr600 revision */
return false;
}
int spi_boot_selected(void)
{
/* SPI boot is not selected in any SPEAr600 revision */
return false;
}
int i2c_boot_selected(void)
{
/* I2C boot is not selected in any SPEAr600 revision */
return false;
}
int mmc_boot_selected(void)
{
return false;
}
void plat_late_init(void)
{
spear_late_init();
}
arch/arm/cpu/arm926ejs/spear/spl.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <init.h>
#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_syscntl.h>
#include <linux/mtd/st_smi.h>
/* Reserve some space to store the BootROM's stack pointer during SPL operation.
* The BSS cannot be used for this purpose because it will be zeroed after
* having stored the pointer, so force the location to the data section.
*/
u32 bootrom_stash_sp __section(".data");
static void ddr_clock_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 clkenb, ddrpll;
clkenb = readl(&misc_p->periph1_clken);
clkenb &= ~PERIPH_MPMCMSK;
clkenb |= PERIPH_MPMC_WE;
/* Intentionally done twice */
writel(clkenb, &misc_p->periph1_clken);
writel(clkenb, &misc_p->periph1_clken);
ddrpll = readl(&misc_p->pll_ctr_reg);
ddrpll &= ~MEM_CLK_SEL_MSK;
#if (CONFIG_DDR_HCLK)
ddrpll |= MEM_CLK_HCLK;
#elif (CONFIG_DDR_2HCLK)
ddrpll |= MEM_CLK_2HCLK;
#elif (CONFIG_DDR_PLL2)
ddrpll |= MEM_CLK_PLL2;
#else
#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
#endif
writel(ddrpll, &misc_p->pll_ctr_reg);
writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
&misc_p->periph1_clken);
}
static void mpmc_init_values(void)
{
u32 i;
u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
u32 *mpmc_val_p = &mpmc_conf_vals[0];
for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
writel(*mpmc_val_p, mpmc_reg_p);
mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
/*
* MPMC controller start
* MPMC waiting for DLLLOCKREG high
*/
writel(0x01000100, &mpmc_reg_p[7]);
while (!(readl(&mpmc_reg_p[3]) & 0x10000))
;
}
static void mpmc_init(void)
{
/* Clock related settings for DDR */
ddr_clock_init();
/*
* DDR pad register bits are different for different SoCs
* Compensation values are also handled separately
*/
plat_ddr_init();
/* Initialize mpmc register values */
mpmc_init_values();
}
static void pll_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
/* Initialize PLLs */
writel(FREQ_332, &misc_p->pll1_frq);
writel(0x1C0A, &misc_p->pll1_cntl);
writel(0x1C0E, &misc_p->pll1_cntl);
writel(0x1C06, &misc_p->pll1_cntl);
writel(0x1C0E, &misc_p->pll1_cntl);
writel(FREQ_332, &misc_p->pll2_frq);
writel(0x1C0A, &misc_p->pll2_cntl);
writel(0x1C0E, &misc_p->pll2_cntl);
writel(0x1C06, &misc_p->pll2_cntl);
writel(0x1C0E, &misc_p->pll2_cntl);
/* wait for pll locks */
while (!(readl(&misc_p->pll1_cntl) & 0x1))
;
while (!(readl(&misc_p->pll2_cntl) & 0x1))
;
}
static void mac_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
&misc_p->periph1_clken);
writel(SYNTH23, &misc_p->gmac_synth_clk);
switch (get_socrev()) {
case SOC_SPEAR600_AA:
case SOC_SPEAR600_AB:
case SOC_SPEAR600_BA:
case SOC_SPEAR600_BB:
case SOC_SPEAR600_BC:
case SOC_SPEAR600_BD:
writel(0x0, &misc_p->gmac_ctr_reg);
break;
case SOC_SPEAR300:
case SOC_SPEAR310:
case SOC_SPEAR320:
writel(0x4, &misc_p->gmac_ctr_reg);
break;
}
writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
&misc_p->periph1_clken);
writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
&misc_p->periph1_rst);
writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
&misc_p->periph1_rst);
}
static void sys_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
struct syscntl_regs *syscntl_p =
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
/* Set system state to SLOW */
writel(SLOW, &syscntl_p->scctrl);
writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
/* Initialize PLLs */
pll_init();
/*
* Ethernet configuration
* To be done only if the tftp boot is not selected already
* Boot code ensures the correct configuration in tftp booting
*/
if (!tftp_boot_selected())
mac_init();
writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
writel(0x555, &misc_p->amba_clk_cfg);
writel(NORMAL, &syscntl_p->scctrl);
/* Wait for system to switch to normal mode */
while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
!= NORMAL)
;
}
/*
* get_socrev
*
* Get SoC Revision.
* @return SOC_SPEARXXX
*/
int get_socrev(void)
{
#if defined(CONFIG_SPEAR600)
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 soc_id = readl(&misc_p->soc_core_id);
u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
if ((pri_socid == 'B') && (sec_socid == 'B'))
return SOC_SPEAR600_BB;
else if ((pri_socid == 'B') && (sec_socid == 'C'))
return SOC_SPEAR600_BC;
else if ((pri_socid == 'B') && (sec_socid == 'D'))
return SOC_SPEAR600_BD;
else if (soc_id == 0)
return SOC_SPEAR600_BA;
else
return SOC_SPEAR_NA;
#elif defined(CONFIG_SPEAR300)
return SOC_SPEAR300;
#elif defined(CONFIG_SPEAR310)
return SOC_SPEAR310;
#elif defined(CONFIG_SPEAR320)
return SOC_SPEAR320;
#endif
}
/*
* SNOR (Serial NOR flash) related functions
*/
static void snor_init(void)
{
struct smi_regs *const smicntl =
(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
&smicntl->smi_cr1);
}
u32 spl_boot_device(void)
{
u32 mode = 0;
if (usb_boot_selected()) {
mode = BOOT_DEVICE_BOOTROM;
} else if (snor_boot_selected()) {
/* SNOR-SMI initialization */
snor_init();
mode = BOOT_DEVICE_NOR;
}
return mode;
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
/*
* If the main boot device (eg. NOR) is empty, try to jump back into the
* BootROM for USB boot process.
*/
if (USB_BOOT_SUPPORTED)
spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
}
void board_init_f(ulong dummy)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
/* Initialize PLLs */
sys_init();
preloader_console_init();
arch_cpu_init();
/* Enable IPs (release reset) */
writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
/* Initialize MPMC */
puts("Configure DDR\n");
mpmc_init();
spear_late_init();
}
/*
* In a few cases (Ethernet, UART or USB boot, we might want to go back into the
* BootROM code right after having initialized a few components like the DRAM).
* The following function is called from SPL common code (board_init_r).
*/
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
/*
* Retrieve the BootROM's stack pointer and jump back to the start of
* the SPL, where we can easily branch back into the BootROM. Don't do
* it right here because SPL might be compiled in Thumb mode while the
* BootROM expects ARM mode.
*/
asm volatile ("ldr r0, =bootrom_stash_sp;"
"ldr r0, [r0];"
"mov sp, r0;"
#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
"blx back_to_bootrom;"
#else
"bl back_to_bootrom;"
#endif
);
return 0;
}
arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*/
#include <common.h>
#if (CONFIG_DDR_PLL2)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
0x00000001,
0x00000000,
0x01000000,
0x00000101,
0x00000001,
0x01000000,
0x00010001,
0x00000100,
0x00010001,
0x00000003,
0x01000201,
0x06000202,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
0x02010106,
0x03000404,
0x02030202,
0x03000204,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x08080a01,
0x0000023f,
0x00040800,
0x00000000,
0x00000f02,
0x00001b1b,
0x7f000000,
0x005f0000,
0x1c040b6a,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x000007ff,
0x00000000,
0x47ec00c8,
0x00c8001f,
0x00000000,
0x0000cd98,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00270000,
0x00250027,
0x00300000,
0x008900b7,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif
arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*/
#include <common.h>
#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
#if (CONFIG_DDR_PLL2)
0x00000001,
0x00000000,
#elif (CONFIG_DDR_2HCLK)
0x02020201,
0x02020202,
#endif
0x01000000,
0x00000101,
0x00000101,
0x01000000,
0x00010001,
0x00000100,
0x01010001,
0x00000201,
0x01000101,
0x06000002,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
0x02010106,
0x03000405,
0x03040202,
0x04000305,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x0a0a0a01,
0x0000023f,
0x00050a00,
0x11000000,
0x00001302,
0x00000A0A,
0x72000000,
0x00550000,
0x2b050e86,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00000a24,
0x43C20000,
0x5b1c00c8,
0x00c8002e,
0x00000000,
0x0001046b,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00210000,
0x00010021,
0x00200000,
0x006c0090,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif
arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*/
#include <common.h>
#if (CONFIG_DDR_HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
0x03030301,
0x03030303,
0x01000000,
0x00000101,
0x00000001,
0x01000000,
0x00010001,
0x00000100,
0x00010001,
0x00000003,
0x01000201,
0x06000202,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
0x02010106,
0x03000404,
0x02020202,
0x03000203,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x08080a01,
0x0000023f,
0x00030600,
0x00000000,
0x00000a02,
0x00001c1c,
0x7f000000,
0x005f0000,
0x12030743,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x0000050e,
0x00000000,
0x2d8900c8,
0x00c80014,
0x00000000,
0x00008236,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00400000,
0x003a0040,
0x00680000,
0x00d80120,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif
arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*/
#include <common.h>
#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
#if (CONFIG_DDR_PLL2)
0x00000001,
0x00000000,
#elif (CONFIG_DDR_2HCLK)
0x02020201,
0x02020202,
#endif
0x01000000,
0x00000101,
0x00000101,
0x01000000,
0x00010001,
0x00000100,
0x01010001,
0x00000201,
0x01000101,
0x06000002,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
#ifdef CONFIG_X600
0x02030206,
#else
0x02010106,
#endif
0x03000405,
0x03040202,
0x04000305,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x0a0a0a01,
0x0000023f,
0x00050a00,
0x11000000,
0x00001302,
0x00000A0A,
#ifdef CONFIG_X600
0x7f000000,
0x005c0000,
#else
0x72000000,
0x00550000,
#endif
0x2b050e86,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00000a24,
0x43C20000,
0x5b1c00c8,
0x00c8002e,
0x00000000,
0x0001046b,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00210000,
0x00010021,
0x00200000,
0x006c0090,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif
arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <config.h>
/*
* platform specific initializations are already done in Xloader
* Initializations already done include
* DDR, PLLs, IP's clock enable and reset release etc
*/
.globl lowlevel_init
lowlevel_init:
mov pc, lr
/* void setfreq(unsigned int device, unsigned int frequency) */
.global setfreq
setfreq:
stmfd sp!,{r14}
stmfd sp!,{r0-r12}
mov r8,sp
ldr sp,SRAM_STACK_V
/* Saving the function arguements for later use */
mov r4,r0
mov r5,r1
/* Putting DDR into self refresh */
ldr r0,DDR_07_V
ldr r1,[r0]
ldr r2,DDR_ACTIVE_V
bic r1, r1, r2
str r1,[r0]
ldr r0,DDR_57_V
ldr r1,[r0]
ldr r2,CYCLES_MASK_V
bic r1, r1, r2
ldr r2,REFRESH_CYCLES_V
orr r1, r1, r2, lsl #16
str r1,[r0]
ldr r0,DDR_07_V
ldr r1,[r0]
ldr r2,SREFRESH_MASK_V
orr r1, r1, r2
str r1,[r0]
/* flush pipeline */
b flush
.align 5
flush:
/* Delay to ensure self refresh mode */
ldr r0,SREFRESH_DELAY_V
delay:
sub r0,r0,#1
cmp r0,#0
bne delay
/* Putting system in slow mode */
ldr r0,SCCTRL_V
mov r1,#2
str r1,[r0]
/* Changing PLL(1/2) frequency */
mov r0,r4
mov r1,r5
cmp r4,#0
beq pll1_freq
/* Change PLL2 (DDR frequency) */
ldr r6,PLL2_FREQ_V
ldr r7,PLL2_CNTL_V
b pll2_freq
pll1_freq:
/* Change PLL1 (CPU frequency) */
ldr r6,PLL1_FREQ_V
ldr r7,PLL1_CNTL_V
pll2_freq:
mov r0,r6
ldr r1,[r0]
ldr r2,PLLFREQ_MASK_V
bic r1,r1,r2
mov r2,r5,lsr#1
orr r1,r1,r2,lsl#24
str r1,[r0]
mov r0,r7
ldr r1,P1C0A_V
str r1,[r0]
ldr r1,P1C0E_V
str r1,[r0]
ldr r1,P1C06_V
str r1,[r0]
ldr r1,P1C0E_V
str r1,[r0]
lock:
ldr r1,[r0]
and r1,r1,#1
cmp r1,#0
beq lock
/* Putting system back to normal mode */
ldr r0,SCCTRL_V
mov r1,#4
str r1,[r0]
/* Putting DDR back to normal */
ldr r0,DDR_07_V
ldr r1,[R0]
ldr r2,SREFRESH_MASK_V
bic r1, r1, r2
str r1,[r0]
ldr r2,DDR_ACTIVE_V
orr r1, r1, r2
str r1,[r0]
/* Delay to ensure self refresh mode */
ldr r0,SREFRESH_DELAY_V
1:
sub r0,r0,#1
cmp r0,#0
bne 1b
mov sp,r8
/* Resuming back to code */
ldmia sp!,{r0-r12}
ldmia sp!,{pc}
SCCTRL_V:
.word 0xfca00000
PLL1_FREQ_V:
.word 0xfca8000C
PLL1_CNTL_V:
.word 0xfca80008
PLL2_FREQ_V:
.word 0xfca80018
PLL2_CNTL_V:
.word 0xfca80014
PLLFREQ_MASK_V:
.word 0xff000000
P1C0A_V:
.word 0x1C0A
P1C0E_V:
.word 0x1C0E
P1C06_V:
.word 0x1C06
SREFRESH_DELAY_V:
.word 0x9999
SRAM_STACK_V:
.word 0xD2800600
DDR_07_V:
.word 0xfc60001c
DDR_ACTIVE_V:
.word 0x01000000
DDR_57_V:
.word 0xfc6000e4
CYCLES_MASK_V:
.word 0xffff0000
REFRESH_CYCLES_V:
.word 0xf0f0
SREFRESH_MASK_V:
.word 0x00010000
.global setfreq_sz
setfreq_sz:
.word setfreq_sz - setfreq
arch/arm/cpu/arm926ejs/spear/spr_misc.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_emi.h>
#include <asm/arch/spr_defs.h>
#define CPU 0
#define DDR 1
#define SRAM_REL 0xD2801000
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET)
static int i2c_read_mac(uchar *buffer);
#endif
int dram_init(void)
{
/* Store complete RAM size and return */
gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
int board_early_init_f()
{
#if defined(CONFIG_ST_SMI)
smi_init();
#endif
return 0;
}
int misc_init_r(void)
{
#if defined(CONFIG_CMD_NET)
uchar mac_id[6];
if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
eth_env_set_enetaddr("ethaddr", mac_id);
#endif
env_set("verify", "n");
#if defined(CONFIG_SPEAR_USBTTY)
env_set("stdin", "usbtty");
env_set("stdout", "usbtty");
env_set("stderr", "usbtty");
#ifndef CONFIG_SYS_NO_DCACHE
dcache_enable();
#endif
#endif
return 0;
}
#ifdef CONFIG_SPEAR_EMI
struct cust_emi_para {
unsigned int tap;
unsigned int tsdp;
unsigned int tdpw;
unsigned int tdpr;
unsigned int tdcs;
};
/* EMI timing setting of m28w640hc of linux kernel */
const struct cust_emi_para emi_timing_m28w640hc = {
.tap = 0x10,
.tsdp = 0x05,
.tdpw = 0x0a,
.tdpr = 0x0a,
.tdcs = 0x05,
};
/* EMI timing setting of bootrom */
const struct cust_emi_para emi_timing_bootrom = {
.tap = 0xf,
.tsdp = 0x0,
.tdpw = 0xff,
.tdpr = 0x111,
.tdcs = 0x02,
};
void spear_emi_init(void)
{
const struct cust_emi_para *p = &emi_timing_m28w640hc;
struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
unsigned int cs;
unsigned int val, tmp;
val = readl(CONFIG_SPEAR_RASBASE);
if (val & EMI_ACKMSK)
tmp = 0x3f;
else
tmp = 0x0;
writel(tmp, &emi_regs_p->ack);
for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
&emi_regs_p->bank_regs[cs].control);
}
}
#endif
int spear_board_init(ulong mach_type)
{
gd->bd->bi_arch_number = mach_type;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
#ifdef CONFIG_SPEAR_EMI
spear_emi_init();
#endif
return 0;
}
#if defined(CONFIG_CMD_NET)
static int i2c_read_mac(uchar *buffer)
{
u8 buf[2];
i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
/* Check if mac in i2c memory is valid */
if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
/* Valid mac address is saved in i2c eeprom */
i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
return 0;
}
return -1;
}
static int write_mac(uchar *mac)
{
u8 buf[2];
buf[0] = (u8)MAGIC_BYTE0;
buf[1] = (u8)MAGIC_BYTE1;
i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
buf[0] = (u8)~MAGIC_BYTE0;
buf[1] = (u8)~MAGIC_BYTE1;
i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
/* check if valid MAC address is saved in I2C EEPROM or not? */
if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
puts("I2C EEPROM written with mac address \n");
return 0;
}
puts("I2C EEPROM writing failed\n");
return -1;
}
#endif
int do_chip_config(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
void (*sram_setfreq) (unsigned int, unsigned int);
unsigned int frequency;
#if defined(CONFIG_CMD_NET)
unsigned char mac[6];
#endif
if ((argc > 3) || (argc < 2))
return cmd_usage(cmdtp);
if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
frequency = simple_strtoul(argv[2], NULL, 0);
if (frequency > 333) {
printf("Frequency is limited to 333MHz\n");
return 1;
}
sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
if (!strcmp(argv[1], "cpufreq")) {
sram_setfreq(CPU, frequency);
printf("CPU frequency changed to %u\n", frequency);
} else {
sram_setfreq(DDR, frequency);
printf("DDR frequency changed to %u\n", frequency);
}
return 0;
#if defined(CONFIG_CMD_NET)
} else if (!strcmp(argv[1], "ethaddr")) {
u32 reg;
char *e, *s = argv[2];
for (reg = 0; reg < 6; ++reg) {
mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
write_mac(mac);
return 0;
#endif
} else if (!strcmp(argv[1], "print")) {
#if defined(CONFIG_CMD_NET)
if (!i2c_read_mac(mac)) {
printf("Ethaddr (from i2c mem) = %pM\n", mac);
} else {
printf("Ethaddr (from i2c mem) = Not set\n");
}
#endif
return 0;
}
return cmd_usage(cmdtp);
}
U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
"configure chip",
"chip_config cpufreq/ddrfreq frequency\n"
#if defined(CONFIG_CMD_NET)
"chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
#endif
"chip_config print");
arch/arm/cpu/arm926ejs/spear/start.S 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
*/
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* The BootROM already initialized its own stack in the [0-0xb00] reserved
* range of the SRAM. The SPL (in _main) will update the stack pointer to
* its own SRAM area (right before the gd section).
*
*************************************************************************
*/
.globl reset
.globl back_to_bootrom
reset:
/*
* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
* UART boot, USB boot): save registers in BootROM's stack and then the
* BootROM's stack pointer in the SPL's data section.
*/
push {r0-r12,lr}
ldr r0, =bootrom_stash_sp
str sp, [r0]
/*
* Flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */
/*
* Enable instruction cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
/*
* Go setup Memory and board specific bits prior to relocation.
* This call is not supposed to return.
*/
b _main /* _main will call board_init_f */
back_to_bootrom:
pop {r0-r12,pc}
arch/arm/cpu/arm926ejs/spear/timer.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_gpt.h>
#include <asm/arch/spr_misc.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
static struct gpt_regs *const gpt_regs_p =
(struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
static struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
DECLARE_GLOBAL_DATA_PTR;
static ulong get_timer_masked(void);
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
int timer_init(void)
{
u32 synth;
/* Prescaler setting */
#if defined(CONFIG_SPEAR3XX)
writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
synth = MISC_GPT4SYNTH;
#elif defined(CONFIG_SPEAR600)
writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
synth = MISC_GPT3SYNTH;
#else
# error Incorrect config. Can only be SPEAR{600|300|310|320}
#endif
writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
&misc_regs_p->periph_clk_cfg);
/* disable timers */
writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
/* load value for free running */
writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
/* auto reload, start timer */
writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
/* Reset the timer */
lastdec = READ_TIMER();
timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
ulong get_timer(ulong base)
{
return (get_timer_masked() / GPT_RESOLUTION) - base;
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
/* tenudelcnt timer tick gives 10 microsecconds delay */
tmo = ((usec / 10) + rndoff) * tenudelcnt;
while ((ulong) (get_timer_masked() - start) < tmo)
;
}
static ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
if (now >= lastdec) {
/* normal mode */
timestamp += now - lastdec;
} else {
/* we have an overflow ... */
timestamp += now + GPT_FREE_RUNNING - lastdec;
}
lastdec = now;
return timestamp;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SPEAR_HZ;
}
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
.text :
{
__start = .;
*(.vectors)
CPUDIR/spear/start.o (.text*)
*(.text*)
} > .sram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} > .sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} > .sram
}
arch/arm/include/asm/arch-spear/clk.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010, STMicroelectronics - All Rights Reserved
* Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
*/
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return 83000000;
}
arch/arm/include/asm/arch-spear/gpio.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*/
#ifndef __ASM_ARCH_SPEAR_GPIO_H
#define __ASM_ARCH_SPEAR_GPIO_H
enum gpio_direction {
GPIO_DIRECTION_IN,
GPIO_DIRECTION_OUT,
};
struct gpio_regs {
u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */
u32 gpiodir; /* 0x400 */
};
#define SPEAR_GPIO_COUNT 8
#define DATA_REG_ADDR(gpio) (1 << (gpio + 2))
#endif /* __ASM_ARCH_SPEAR_GPIO_H */
arch/arm/include/asm/arch-spear/hardware.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2009, STMicroelectronics - All Rights Reserved
* Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
*/
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define CONFIG_SYS_USBD_BASE 0xE1100000
#define CONFIG_SYS_PLUG_BASE 0xE1200000
#define CONFIG_SYS_FIFO_BASE 0xE1000800
#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
#define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
#define CONFIG_SYS_SMI_BASE 0xFC000000
#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
#define CONFIG_SPEAR_TIMERBASE 0xFC800000
#define CONFIG_SPEAR_MISCBASE 0xFCA80000
#define CONFIG_SPEAR_ETHBASE 0xE0800000
#define CONFIG_SPEAR_MPMCBASE 0xFC600000
#define CONFIG_SSP1_BASE 0xD0100000
#define CONFIG_SSP2_BASE 0xD0180000
#define CONFIG_SSP3_BASE 0xD8180000
#define CONFIG_GPIO_BASE 0xD8100000
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_FSMC_BASE 0xD1800000
#define CONFIG_FSMC_NAND_BASE 0xD2000000
#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000
#define CONFIG_SPEAR_BOOTSTRAPSHFT 16
#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB
#define CONFIG_SPEAR_ONLYSNORBOOT 0xA
#define CONFIG_SPEAR_NORNANDBOOT 0xB
#define CONFIG_SPEAR_NORNAND8BOOT 0x8
#define CONFIG_SPEAR_NORNAND16BOOT 0x9
#define CONFIG_SPEAR_USBBOOT 0x8
#define CONFIG_SPEAR_MPMCREGS 100
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_FSMC_BASE 0x94000000
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_FSMC_BASE 0x44000000
#undef CONFIG_SYS_NAND_CLE
#undef CONFIG_SYS_NAND_ALE
#define CONFIG_SYS_NAND_CLE (1 << 17)
#define CONFIG_SYS_NAND_ALE (1 << 16)
#define CONFIG_SPEAR_EMIBASE 0x4F000000
#define CONFIG_SPEAR_RASBASE 0xB4000000
#define CONFIG_SYS_MACB0_BASE 0xB0000000
#define CONFIG_SYS_MACB1_BASE 0xB0800000
#define CONFIG_SYS_MACB2_BASE 0xB1000000
#define CONFIG_SYS_MACB3_BASE 0xB1800000
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_FSMC_BASE 0x4C000000
#define CONFIG_SPEAR_EMIBASE 0x40000000
#define CONFIG_SPEAR_RASBASE 0xB3000000
#define CONFIG_SYS_MACB0_BASE 0xAA000000
#endif
#endif /* _ASM_ARCH_HARDWARE_H */
arch/arm/include/asm/arch-spear/spr_defs.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#ifndef __SPR_DEFS_H__
#define __SPR_DEFS_H__
extern int spear_board_init(ulong);
extern void setfreq(unsigned int, unsigned int);
extern unsigned int setfreq_sz;
void plat_ddr_init(void);
void spear_late_init(void);
int snor_boot_selected(void);
int nand_boot_selected(void);
int pnor_boot_selected(void);
int usb_boot_selected(void);
int uart_boot_selected(void);
int tftp_boot_selected(void);
int i2c_boot_selected(void);
int spi_boot_selected(void);
int mmc_boot_selected(void);
extern u32 mpmc_conf_vals[];
struct chip_data {
int cpufreq;
int dramfreq;
int dramtype;
uchar version[32];
};
/* HW mac id in i2c memory definitions */
#define MAGIC_OFF 0x0
#define MAGIC_LEN 0x2
#define MAGIC_BYTE0 0x55
#define MAGIC_BYTE1 0xAA
#define MAC_OFF 0x2
#define MAC_LEN 0x6
#define PNOR_WIDTH_8 0
#define PNOR_WIDTH_16 1
#define PNOR_WIDTH_32 2
#define PNOR_WIDTH_NUM 3
#define PNOR_WIDTH_SEARCH 0xff
#endif
arch/arm/include/asm/arch-spear/spr_emi.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
*/
#ifndef __SPEAR_EMI_H__
#define __SPEAR_EMI_H__
#ifdef CONFIG_SPEAR_EMI
struct emi_bank_regs {
u32 tap;
u32 tsdp;
u32 tdpw;
u32 tdpr;
u32 tdcs;
u32 control;
};
struct emi_regs {
struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
u32 tout;
u32 ack;
u32 irq;
};
#define EMI_ACKMSK 0x40
/* control register definitions */
#define EMI_CNTL_ENBBYTEW (1 << 2)
#define EMI_CNTL_ENBBYTER (1 << 3)
#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
#endif
#endif
arch/arm/include/asm/arch-spear/spr_gpt.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#ifndef _SPR_GPT_H
#define _SPR_GPT_H
struct gpt_regs {
u8 reserved[0x80];
u32 control;
u32 status;
u32 compare;
u32 count;
u32 capture_re;
u32 capture_fe;
};
/*
* TIMER_CONTROL register settings
*/
#define GPT_PRESCALER_MASK 0x000F
#define GPT_PRESCALER_1 0x0000
#define GPT_PRESCALER_2 0x0001
#define GPT_PRESCALER_4 0x0002
#define GPT_PRESCALER_8 0x0003
#define GPT_PRESCALER_16 0x0004
#define GPT_PRESCALER_32 0x0005
#define GPT_PRESCALER_64 0x0006
#define GPT_PRESCALER_128 0x0007
#define GPT_PRESCALER_256 0x0008
#define GPT_MODE_SINGLE_SHOT 0x0010
#define GPT_MODE_AUTO_RELOAD 0x0000
#define GPT_ENABLE 0x0020
#define GPT_CAPT_MODE_MASK 0x00C0
#define GPT_CAPT_MODE_NONE 0x0000
#define GPT_CAPT_MODE_RE 0x0040
#define GPT_CAPT_MODE_FE 0x0080
#define GPT_CAPT_MODE_BOTH 0x00C0
#define GPT_INT_MATCH 0x0100
#define GPT_INT_FE 0x0200
#define GPT_INT_RE 0x0400
/*
* TIMER_STATUS register settings
*/
#define GPT_STS_MATCH 0x0001
#define GPT_STS_FE 0x0002
#define GPT_STS_RE 0x0004
/*
* TIMER_COMPARE register settings
*/
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
#define CONFIG_SPEAR_HZ 1000
#define CONFIG_SPEAR_HZ_CLOCK 8300000
#endif
arch/arm/include/asm/arch-spear/spr_misc.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#ifndef _SPR_MISC_H
#define _SPR_MISC_H
struct misc_regs {
u32 auto_cfg_reg; /* 0x0 */
u32 armdbg_ctr_reg; /* 0x4 */
u32 pll1_cntl; /* 0x8 */
u32 pll1_frq; /* 0xc */
u32 pll1_mod; /* 0x10 */
u32 pll2_cntl; /* 0x14 */
u32 pll2_frq; /* 0x18 */
u32 pll2_mod; /* 0x1C */
u32 pll_ctr_reg; /* 0x20 */
u32 amba_clk_cfg; /* 0x24 */
u32 periph_clk_cfg; /* 0x28 */
u32 periph1_clken; /* 0x2C */
u32 soc_core_id; /* 0x30 */
u32 ras_clken; /* 0x34 */
u32 periph1_rst; /* 0x38 */
u32 periph2_rst; /* 0x3C */
u32 ras_rst; /* 0x40 */
u32 prsc1_clk_cfg; /* 0x44 */
u32 prsc2_clk_cfg; /* 0x48 */
u32 prsc3_clk_cfg; /* 0x4C */
u32 amem_cfg_ctrl; /* 0x50 */
u32 expi_clk_cfg; /* 0x54 */
u32 reserved_1; /* 0x58 */
u32 clcd_synth_clk; /* 0x5C */
u32 irda_synth_clk; /* 0x60 */
u32 uart_synth_clk; /* 0x64 */
u32 gmac_synth_clk; /* 0x68 */
u32 ras_synth1_clk; /* 0x6C */
u32 ras_synth2_clk; /* 0x70 */
u32 ras_synth3_clk; /* 0x74 */
u32 ras_synth4_clk; /* 0x78 */
u32 arb_icm_ml1; /* 0x7C */
u32 arb_icm_ml2; /* 0x80 */
u32 arb_icm_ml3; /* 0x84 */
u32 arb_icm_ml4; /* 0x88 */
u32 arb_icm_ml5; /* 0x8C */
u32 arb_icm_ml6; /* 0x90 */
u32 arb_icm_ml7; /* 0x94 */
u32 arb_icm_ml8; /* 0x98 */
u32 arb_icm_ml9; /* 0x9C */
u32 dma_src_sel; /* 0xA0 */
u32 uphy_ctr_reg; /* 0xA4 */
u32 gmac_ctr_reg; /* 0xA8 */
u32 port_bridge_ctrl; /* 0xAC */
u32 reserved_2[4]; /* 0xB0--0xBC */
u32 prc1_ilck_ctrl_reg; /* 0xC0 */
u32 prc2_ilck_ctrl_reg; /* 0xC4 */
u32 prc3_ilck_ctrl_reg; /* 0xC8 */
u32 prc4_ilck_ctrl_reg; /* 0xCC */
u32 prc1_intr_ctrl_reg; /* 0xD0 */
u32 prc2_intr_ctrl_reg; /* 0xD4 */
u32 prc3_intr_ctrl_reg; /* 0xD8 */
u32 prc4_intr_ctrl_reg; /* 0xDC */
u32 powerdown_cfg_reg; /* 0xE0 */
u32 ddr_1v8_compensation; /* 0xE4 */
u32 ddr_2v5_compensation; /* 0xE8 */
u32 core_3v3_compensation; /* 0xEC */
u32 ddr_pad; /* 0xF0 */
u32 bist1_ctr_reg; /* 0xF4 */
u32 bist2_ctr_reg; /* 0xF8 */
u32 bist3_ctr_reg; /* 0xFC */
u32 bist4_ctr_reg; /* 0x100 */
u32 bist5_ctr_reg; /* 0x104 */
u32 bist1_rslt_reg; /* 0x108 */
u32 bist2_rslt_reg; /* 0x10C */
u32 bist3_rslt_reg; /* 0x110 */
u32 bist4_rslt_reg; /* 0x114 */
u32 bist5_rslt_reg; /* 0x118 */
u32 syst_error_reg; /* 0x11C */
u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
u32 ras_gpp1_in; /* 0x8000 */
u32 ras_gpp2_in; /* 0x8004 */
u32 ras_gpp1_out; /* 0x8008 */
u32 ras_gpp2_out; /* 0x800C */
};
/* SYNTH_CLK value*/
#define SYNTH23 0x00020003
/* PLLx_FRQ value */
#if defined(CONFIG_SPEAR3XX)
#define FREQ_332 0xA600010C
#define FREQ_266 0x8500010C
#elif defined(CONFIG_SPEAR600)
#define FREQ_332 0xA600010F
#define FREQ_266 0x8500010F
#endif
/* PLL_CTR_REG */
#define MEM_CLK_SEL_MSK 0x70000000
#define MEM_CLK_HCLK 0x00000000
#define MEM_CLK_2HCLK 0x10000000
#define MEM_CLK_PLL2 0x30000000
#define EXPI_CLK_CFG_LOW_COMPR 0x2000
#define EXPI_CLK_CFG_CLK_EN 0x0400
#define EXPI_CLK_CFG_RST 0x0200
#define EXPI_CLK_SYNT_EN 0x0010
#define EXPI_CLK_CFG_SEL_PLL2 0x0004
#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
#define PLL2_CNTL_6UA 0x1c00
#define PLL2_CNTL_SAMPLE 0x0008
#define PLL2_CNTL_ENABLE 0x0004
#define PLL2_CNTL_RESETN 0x0002
#define PLL2_CNTL_LOCK 0x0001
/* AUTO_CFG_REG value */
#define MISC_SOCCFGMSK 0x0000003F
#define MISC_SOCCFG30 0x0000000C
#define MISC_SOCCFG31 0x0000000D
#define MISC_NANDDIS 0x00020000
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
#define CONFIG_SPEAR_UART48M 0
#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
/* PRSC_CLK_CFG value */
/*
* Fout = Fin / (2^(N+1) * (M + 1))
*/
#define MISC_PRSC_N_1 0x00001000
#define MISC_PRSC_M_9 0x00000009
#define MISC_PRSC_N_4 0x00004000
#define MISC_PRSC_M_399 0x0000018F
#define MISC_PRSC_N_6 0x00006000
#define MISC_PRSC_M_2593 0x00000A21
#define MISC_PRSC_M_124 0x0000007C
#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9)
/* PERIPH1_CLKEN, PERIPH1_RST value */
#define MISC_USBDENB 0x01000000
#define MISC_ETHENB 0x00800000
#define MISC_SMIENB 0x00200000
#define MISC_GPIO3ENB 0x00040000
#define MISC_GPT3ENB 0x00010000
#define MISC_SSP3ENB 0x00004000
#define MISC_GPIO4ENB 0x00002000
#define MISC_GPT2ENB 0x00000800
#define MISC_FSMCENB 0x00000200
#define MISC_I2CENB 0x00000080
#define MISC_SSP2ENB 0x00000040
#define MISC_SSP1ENB 0x00000020
#define MISC_UART0ENB 0x00000008
/* PERIPH_CLK_CFG */
#define XTALTIMEEN 0x00000001
#define PLLTIMEEN 0x00000002
#define CLCDCLK_SYNTH 0x00000000
#define CLCDCLK_48MHZ 0x00000004
#define CLCDCLK_EXT 0x00000008
#define UARTCLK_MASK (0x1 << 4)
#define UARTCLK_48MHZ 0x00000000
#define UARTCLK_SYNTH 0x00000010
#define IRDACLK_48MHZ 0x00000000
#define IRDACLK_SYNTH 0x00000020
#define IRDACLK_EXT 0x00000040
#define RTC_DISABLE 0x00000080
#define GPT1CLK_48MHZ 0x00000000
#define GPT1CLK_SYNTH 0x00000100
#define GPT2CLK_48MHZ 0x00000000
#define GPT2CLK_SYNTH 0x00000200
#define GPT3CLK_48MHZ 0x00000000
#define GPT3CLK_SYNTH 0x00000400
#define GPT4CLK_48MHZ 0x00000000
#define GPT4CLK_SYNTH 0x00000800
#define GPT5CLK_48MHZ 0x00000000
#define GPT5CLK_SYNTH 0x00001000
#define GPT1_FREEZE 0x00002000
#define GPT2_FREEZE 0x00004000
#define GPT3_FREEZE 0x00008000
#define GPT4_FREEZE 0x00010000
#define GPT5_FREEZE 0x00020000
/* PERIPH1_CLKEN bits */
#define PERIPH_ARM1_WE 0x00000001
#define PERIPH_ARM1 0x00000002
#define PERIPH_ARM2 0x00000004
#define PERIPH_UART1 0x00000008
#define PERIPH_UART2 0x00000010
#define PERIPH_SSP1 0x00000020
#define PERIPH_SSP2 0x00000040
#define PERIPH_I2C 0x00000080
#define PERIPH_JPEG 0x00000100
#define PERIPH_FSMC 0x00000200
#define PERIPH_FIRDA 0x00000400
#define PERIPH_GPT4 0x00000800
#define PERIPH_GPT5 0x00001000
#define PERIPH_GPIO4 0x00002000
#define PERIPH_SSP3 0x00004000
#define PERIPH_ADC 0x00008000
#define PERIPH_GPT3 0x00010000
#define PERIPH_RTC 0x00020000
#define PERIPH_GPIO3 0x00040000
#define PERIPH_DMA 0x00080000
#define PERIPH_ROM 0x00100000
#define PERIPH_SMI 0x00200000
#define PERIPH_CLCD 0x00400000
#define PERIPH_GMAC 0x00800000
#define PERIPH_USBD 0x01000000
#define PERIPH_USBH1 0x02000000
#define PERIPH_USBH2 0x04000000
#define PERIPH_MPMC 0x08000000
#define PERIPH_RAMW 0x10000000
#define PERIPH_MPMC_EN 0x20000000
#define PERIPH_MPMC_WE 0x40000000
#define PERIPH_MPMCMSK 0x60000000
#define PERIPH_CLK_ALL 0x0FFFFFF8
#define PERIPH_RST_ALL 0x00000004
/* DDR_PAD values */
#define DDR_PAD_CNF_MSK 0x0000ffff
#define DDR_PAD_SW_CONF 0x00060000
#define DDR_PAD_SSTL_SEL 0x00000001
#define DDR_PAD_DRAM_TYPE 0x00008000
/* DDR_COMP values */
#define DDR_COMP_ACCURATE 0x00000010
/* SoC revision stuff */
#define SOC_PRI_SHFT 16
#define SOC_SEC_SHFT 8
/* Revision definitions */
#define SOC_SPEAR_NA 0
/*
* The definitons have started from
* 101 for SPEAr6xx
* 201 for SPEAr3xx
* 301 for SPEAr13xx
*/
#define SOC_SPEAR600_AA 101
#define SOC_SPEAR600_AB 102
#define SOC_SPEAR600_BA 103
#define SOC_SPEAR600_BB 104
#define SOC_SPEAR600_BC 105
#define SOC_SPEAR600_BD 106
#define SOC_SPEAR300 201
#define SOC_SPEAR310 202
#define SOC_SPEAR320 203
extern int get_socrev(void);
int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif
arch/arm/include/asm/arch-spear/spr_ssp.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*/
#ifndef _SPR_SSP_H
#define _SPR_SSP_H
struct ssp_regs {
u32 sspcr0;
u32 sspcr1;
u32 sspdr;
u32 sspsr;
u32 sspcpsr;
u32 sspimsc;
u32 sspicr;
u32 sspdmacr;
};
#define SSPCR0_FRF_MOT_SPI 0x0000
#define SSPCR0_DSS_16BITS 0x000f
#define SSPCR1_SSE 0x0002
#define SSPSR_TNF 0x2
#define SSPSR_TFE 0x1
#endif
arch/arm/include/asm/arch-spear/spr_syscntl.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
*/
#ifndef __SYSCTRL_H
#define __SYSCTRL_H
struct syscntl_regs {
u32 scctrl;
u32 scsysstat;
u32 scimctrl;
u32 scimsysstat;
u32 scxtalctrl;
u32 scpllctrl;
u32 scpllfctrl;
u32 scperctrl0;
u32 scperctrl1;
u32 scperen;
u32 scperdis;
const u32 scperclken;
const u32 scperstat;
};
#define MODE_SHIFT 0x00000003
#define NORMAL 0x00000004
#define SLOW 0x00000002
#define DOZE 0x00000001
#define SLEEP 0x00000000
#define PLL_TIM 0x01FFFFFF
#endif
arch/arm/mach-at91/Kconfig
浏览文件 @ bfb5bfa3
......@@ -69,10 +69,6 @@ choice
prompt "Atmel AT91 board select"
optional
config TARGET_AT91RM9200EK
bool "Atmel AT91RM9200 evaluation kit"
select CPU_ARM920T
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
select AT91SAM9260
......@@ -307,7 +303,6 @@ config ATMEL_SFR
config SYS_SOC
default "at91"
source "board/atmel/at91rm9200ek/Kconfig"
source "board/atmel/at91sam9260ek/Kconfig"
source "board/atmel/at91sam9261ek/Kconfig"
source "board/atmel/at91sam9263ek/Kconfig"
......
arch/arm/mach-kirkwood/Kconfig
浏览文件 @ bfb5bfa3
......@@ -53,9 +53,6 @@ config TARGET_GOFLEXHOME
config TARGET_NAS220
bool "BlackArmor NAS220"
config TARGET_NSA310S
bool "Zyxel NSA310S"
config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
......@@ -83,7 +80,6 @@ source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
......
arch/m68k/Kconfig
浏览文件 @ bfb5bfa3
......@@ -65,12 +65,6 @@ config MCF5227x
select DM_SERIAL
bool
config MCF547x_8x
select OF_CONTROL
select DM
select DM_SERIAL
bool
# processor type
config M5208
bool
......@@ -137,14 +131,6 @@ config M52277
bool
select MCF5227x
config M547x
bool
select MCF547x_8x
config M548x
bool
select MCF547x_8x
choice
prompt "Target select"
optional
......@@ -217,14 +203,6 @@ config TARGET_M54455EVB
bool "Support M54455EVB"
select M54455
config TARGET_M5475EVB
bool "Support M5475EVB"
select M547x
config TARGET_M5485EVB
bool "Support M5485EVB"
select M548x
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
......@@ -252,8 +230,6 @@ source "board/freescale/m5373evb/Kconfig"
source "board/freescale/m54418twr/Kconfig"
source "board/freescale/m54451evb/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
source "board/freescale/m548xevb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
......
arch/m68k/Makefile
浏览文件 @ bfb5bfa3
......@@ -19,14 +19,12 @@ cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC
cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC
cpuflags-$(CONFIG_MCF547x_8x) := -mcpu=5485 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
ldflags-$(CONFIG_MCF5441x) := --got=single
ldflags-$(CONFIG_MCF5445x) := --got=single
ldflags-$(CONFIG_MCF547x_8x) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
......
arch/m68k/cpu/mcf547x_8x/Makefile 已删除 100644 → 0
浏览文件 @ 7e58a3a1
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
arch/m68k/cpu/mcf547x_8x/cpu.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
out_be16(&gptmr->pre, 10);
out_be16(&gptmr->cnt, 1);
/* enable watchdog, set timeout to 0 and wait */
out_8(&gptmr->mode, GPT_TMS_SGPIO);
out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
/* we don't return! */
return 1;
};
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
siu_t *siu = (siu_t *) MMAP_SIU;
u16 id = 0;
puts("CPU: ");
switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
case 0x0C:
id = 5485;
break;
case 0x0D:
id = 5484;
break;
case 0x0E:
id = 5483;
break;
case 0x0F:
id = 5482;
break;
case 0x10:
id = 5481;
break;
case 0x11:
id = 5480;
break;
case 0x12:
id = 5475;
break;
case 0x13:
id = 5474;
break;
case 0x14:
id = 5473;
break;
case 0x15:
id = 5472;
break;
case 0x16:
id = 5471;
break;
case 0x17:
id = 5470;
break;
}
if (id) {
char buf1[32], buf2[32];
printf("Freescale MCF%d\n", id);
printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk));
}
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
#if defined(CONFIG_HW_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void hw_watchdog_reset(void)
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
out_8(&gptmr->ocpw, 0xa5);
}
int watchdog_disable(void)
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
out_8(&gptmr->mode, 0);
out_8(&gptmr->ctrl, 0);
puts("WATCHDOG:disabled\n");
return (0);
}
int watchdog_init(void)
{
gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
out_8(&gptmr->mode, GPT_TMS_SGPIO);
out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
puts("WATCHDOG:enabled\n");
return (0);
}
#endif /* CONFIG_HW_WATCHDOG */
#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers. To override,
* create a board-specific function called:
* int board_eth_init(struct bd_info *bis)
*/
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FSLDMAFEC)
mcdmafec_initialize(bis);
#endif
#if defined(CONFIG_MCFFEC)
mcffec_initialize(bis);
#endif
return 0;
}
#endif
arch/m68k/cpu/mcf547x_8x/cpu_init.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <MCD_dma.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/immap.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#include <asm/fsl_mcdmafec.h>
#endif
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
out_be32(&xlbarb->adrto, 0x2000);
out_be32(&xlbarb->datto, 0x2500);
out_be32(&xlbarb->busto, 0x3000);
out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
/* Master Priority Enable */
out_be32(&xlbarb->prien, 0xff);
out_be32(&xlbarb->pri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_SYS_I2C_FSL
out_be16(&gpio->par_feci2cirq,
GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
#endif
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
MCD_RELOC_TASKS);
#endif
return (0);
}
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
/* Setup Ports: */
switch (port) {
case 0:
out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
break;
case 1:
out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
break;
case 2:
out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
break;
case 3:
out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
break;
}
clrbits_8(pscsicr, 0x07);
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 fec0_base;
if (fec_get_base_addr(0, &fec0_base))
return -1;
if (setclear) {
if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2cirq, 0xf000);
else
setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
} else {
if (info->iobase == fec0_base)
clrbits_be16(&gpio->par_feci2cirq, 0xf000);
else
clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
}
return 0;
}
#endif
arch/m68k/cpu/mcf547x_8x/interrupts.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/* CPU specific interrupt routine */
#include <common.h>
#include <irq_func.h>
#include <asm/immap.h>
#include <asm/io.h>
int interrupt_init(void)
{
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
setbits_be32(&intp->imrh0, 0xffffffff);
setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
}
#if defined(CONFIG_SLTTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
arch/m68k/cpu/mcf547x_8x/pci.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/*
* PCI Configuration space access support
*/
#include <common.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/immap.h>
#include <linux/delay.h>
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
#define PCI_OP(rw, size, type, op, mask) \
int pci_##rw##_cfg_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 addr = 0; \
u16 cfg_type = 0; \
addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
out_be32(hose->cfg_addr, addr); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
__asm__ __volatile__("nop"); \
__asm__ __volatile__("nop"); \
out_be32(hose->cfg_addr, addr & 0x7fffffff); \
return 0; \
}
PCI_OP(read, byte, u8 *, in_8, 3)
PCI_OP(read, word, u16 *, in_le16, 2)
PCI_OP(write, byte, u8, out_8, 3)
PCI_OP(write, word, u16, out_le16, 2)
PCI_OP(write, dword, u32, out_le32, 0)
int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
int offset, u32 * val)
{
u32 addr;
u32 tmpv;
u32 mask = 2; /* word access */
/* Read lower 16 bits */
addr = ((offset & 0xfc) | (dev) | 0x80000000);
out_be32(hose->cfg_addr, addr);
*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
__asm__ __volatile__("nop");
out_be32(hose->cfg_addr, addr & 0x7fffffff);
/* Read upper 16 bits */
offset += 2;
addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
out_be32(hose->cfg_addr, addr);
tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
__asm__ __volatile__("nop");
out_be32(hose->cfg_addr, addr & 0x7fffffff);
/* combine results into dword value */
*val = (tmpv << 16) | *val;
return 0;
}
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
pci_t *pci = (pci_t *) MMAP_PCI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */
out_be16(&gpio->par_pcibg,
GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
GPIO_PAR_PCIBG_PCIBG4(3));
out_be16(&gpio->par_pcibr,
GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
GPIO_PAR_PCIBR_PCIBR4(3));
/* Assert reset bit */
setbits_be32(&pci->gscr, PCI_GSCR_PR);
out_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
out_be32(&pci->iw0btar,
CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
out_be32(&pci->iw1btar,
CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
out_be32(&pci->iw2btar,
CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
out_be32(&pci->iwcr,
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
#endif
#ifdef CONFIG_SYS_PCI_BAR1
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
#endif
/* Deassert reset bit */
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */
arch/m68k/cpu/mcf547x_8x/slicetimer.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <init.h>
#include <irq_func.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/timer.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static ulong timestamp;
#if defined(CONFIG_SLTTMR)
#ifndef CONFIG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
#endif
extern void dtimer_intr_setup(void);
void __udelay(unsigned long usec)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
u32 now, freq;
/* 1 us period */
freq = CONFIG_SYS_TIMER_PRESCALER;
/* Disable */
out_be32(&timerp->cr, 0);
out_be32(&timerp->tcnt, usec * freq);
out_be32(&timerp->cr, SLT_CR_TEN);
now = in_be32(&timerp->cnt);
while (now != 0)
now = in_be32(&timerp->cnt);
setbits_be32(&timerp->sr, SLT_SR_ST);
out_be32(&timerp->cr, 0);
}
void dtimer_interrupt(void *not_used)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
/* check for timer interrupt asserted */
if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
setbits_be32(&timerp->sr, SLT_SR_ST);
timestamp++;
return;
}
}
int timer_init(void)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
/* disable timer */
out_be32(&timerp->cr, 0);
out_be32(&timerp->tcnt, 0);
/* clear status */
out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
/* initialize and enable timer interrupt */
irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
/* Interrupt every ms */
out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and
enable timer and interrupt */
out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
return 0;
}
ulong get_timer(ulong base)
{
return (timestamp - base);
}
#endif /* CONFIG_SLTTMR */
arch/m68k/cpu/mcf547x_8x/speed.c 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
}
arch/m68k/cpu/mcf547x_8x/start.S 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include "version.h"
#include <asm/cache.h>
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
vector02_0F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18_1F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CONFIG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
movec %d0, %RAMBAR1
move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
move.c %d0, %MBAR
/* invalidate and disable cache */
move.l #0x01040100, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
/* put relocation table address to a5 */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
move.l #board_init_f_alloc_reserve, %a1
jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
move.l %sp, %fp
/* initialize reserved area */
move.l %d0, -(%sp)
move.l #board_init_f_init_reserve, %a1
jsr (%a1)
/* run low-level CPU init code (from flash) */
jbsr cpu_init_f
/* run low-level board init code (from flash) */
clr.l %sp@-
jbsr board_init_f
/* board_init_f() does not return */
/******************************************************************************/
/*
* void relocate_code(addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/******************************************************************************/
/* exception code */
.globl _fault
_fault:
bra _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/******************************************************************************/
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
.align 4
arch/m68k/dts/M5475AFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475AFE";
compatible = "fsl,M5475AFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475BFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475BFE";
compatible = "fsl,M5475BFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475CFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475CFE";
compatible = "fsl,M5475CFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475DFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475DFE";
compatible = "fsl,M5475DFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475EFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475EFE";
compatible = "fsl,M5475EFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475FFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475FFE";
compatible = "fsl,M5475FFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5475GFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5475GFE";
compatible = "fsl,M5475GFE";
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485AFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485AFE";
compatible = "fsl,M5485AFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485BFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485BFE";
compatible = "fsl,M5485BFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485CFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485CFE";
compatible = "fsl,M5485CFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485DFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485DFE";
compatible = "fsl,M5485DFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485EFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485EFE";
compatible = "fsl,M5485EFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485FFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485FFE";
compatible = "fsl,M5485FFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485GFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485GFE";
compatible = "fsl,M5485GFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/M5485HFE.dts 已删除 100644 → 0
浏览文件 @ 7e58a3a1
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485HFE";
compatible = "fsl,M5485HFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};
arch/m68k/dts/Makefile
浏览文件 @ bfb5bfa3
......@@ -32,21 +32,6 @@ dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
M54455EVB_i66.dtb
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
M5475BFE.dtb \
M5475CFE.dtb \
M5475DFE.dtb \
M5475EFE.dtb \
M5475FFE.dtb \
M5475GFE.dtb
dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
M5485BFE.dtb \
M5485CFE.dtb \
M5485DFE.dtb \
M5485EFE.dtb \
M5485FFE.dtb \
M5485GFE.dtb \
M5485HFE.dtb
targets += $(dtb-y)
......
arch/m68k/include/asm/cache.h
浏览文件 @ bfb5bfa3
......@@ -19,7 +19,7 @@
#define CONFIG_CF_V3
#endif
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
#if defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
......
arch/m68k/include/asm/coldfire/dspi.h
浏览文件 @ bfb5bfa3
......@@ -20,14 +20,8 @@ typedef struct dspi {
u32 tfr; /* 0x34 - PUSHR */
u16 resv1; /* 0x38 */
u16 rfr; /* 0x3A - POPR */
#ifdef CONFIG_MCF547x_8x
u32 tfdr[4]; /* 0x3C */
u8 resv2[0x30]; /* 0x40 */
u32 rfdr[4]; /* 0x7C */
#else
u32 tfdr[16]; /* 0x3C */
u32 rfdr[16]; /* 0x7C */
#endif
} dspi_t;
/* Module configuration */
......
arch/m68k/include/asm/coldfire/eport.h
浏览文件 @ bfb5bfa3
......@@ -11,18 +11,6 @@
/* Edge Port Module (EPORT) */
typedef struct eport {
#ifdef CONFIG_MCF547x_8x
u16 par; /* 0x00 */
u16 res0; /* 0x02 */
u8 ddr; /* 0x04 */
u8 ier; /* 0x05 */
u16 res1; /* 0x06 */
u8 dr; /* 0x08 */
u8 pdr; /* 0x09 */
u16 res2; /* 0x0A */
u8 fr; /* 0x0C */
u8 res3[3]; /* 0x0D */
#else
u16 par; /* 0x00 Pin Assignment */
u8 ddr; /* 0x02 Data Direction */
u8 ier; /* 0x03 Interrupt Enable */
......@@ -30,7 +18,6 @@ typedef struct eport {
u8 pdr; /* 0x05 Pin Data */
u8 fr; /* 0x06 Flag */
u8 res0;
#endif
} eport_t;
/* EPPAR */
......
arch/m68k/include/asm/coldfire/intctrl.h
浏览文件 @ bfb5bfa3
......@@ -11,7 +11,7 @@
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
defined(CONFIG_M547x) || defined(CONFIG_M548x)
defined(CONFIG_M547x)
# define CONFIG_SYS_CF_INTC_REG1
#endif
......
arch/m68k/include/asm/fec.h
浏览文件 @ bfb5bfa3
......@@ -337,13 +337,8 @@ typedef struct fec {
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
#ifdef CONFIG_MCF547x_8x
typedef struct fec_info_dma fec_info_t;
#define FEC_T fecdma_t
#else
typedef struct fec_info_s fec_info_t;
#define FEC_T fec_t
#endif
int fecpin_setclear(fec_info_t *info, int setclear);
int mii_discover_phy(fec_info_t *info);
......
arch/m68k/include/asm/immap.h
浏览文件 @ bfb5bfa3
......@@ -412,51 +412,4 @@
#endif
#endif /* CONFIG_M547x */
#ifdef CONFIG_M548x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6
#define FEC0_TX_PRIORITY 7
#define FEC0_RX_INIT 16
#define FEC0_TX_INIT 17
#define FEC1_RX_TASK 2
#define FEC1_TX_TASK 3
#define FEC1_RX_PRIORITY 6
#define FEC1_TX_PRIORITY 7
#define FEC1_RX_INIT 30
#define FEC1_TX_INIT 31
#endif
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
/* Timer */
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M548x */
#endif /* __IMMAP_H */
arch/m68k/include/asm/immap_547x_8x.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* MCF547x_8x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#ifndef __IMMAP_547x_8x__
#define __IMMAP_547x_8x__
#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500)
#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700)
#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800)
#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900)
#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910)
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00)
#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00)
#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00)
#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700)
#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800)
#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900)
#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00)
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00)
#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000)
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800)
#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800)
#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000)
#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000)
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
typedef struct siu {
u32 mbar; /* 0x00 */
u32 drv; /* 0x04 */
u32 rsvd1[2]; /* 0x08 - 0x1F */
u32 sbcr; /* 0x10 */
u32 rsvd2[3]; /* 0x14 - 0x1F */
u32 cs0cfg; /* 0x20 */
u32 cs1cfg; /* 0x24 */
u32 cs2cfg; /* 0x28 */
u32 cs3cfg; /* 0x2C */
u32 rsvd3[2]; /* 0x30 - 0x37 */
u32 secsacr; /* 0x38 */
u32 rsvd4[2]; /* 0x3C - 0x43 */
u32 rsr; /* 0x44 */
u32 rsvd5[2]; /* 0x48 - 0x4F */
u32 jtagid; /* 0x50 */
} siu_t;
typedef struct sdram {
u32 mode; /* 0x00 */
u32 ctrl; /* 0x04 */
u32 cfg1; /* 0x08 */
u32 cfg2; /* 0x0c */
} sdram_t;
typedef struct xlb_arb {
u32 cfg; /* 0x240 */
u32 ver; /* 0x244 */
u32 sr; /* 0x248 */
u32 imr; /* 0x24c */
u32 adrcap; /* 0x250 */
u32 sigcap; /* 0x254 */
u32 adrto; /* 0x258 */
u32 datto; /* 0x25c */
u32 busto; /* 0x260 */
u32 prien; /* 0x264 */
u32 pri; /* 0x268 */
} xlbarb_t;
typedef struct gptmr {
u8 ocpw;
u8 octict;
u8 ctrl;
u8 mode;
u16 pre; /* Prescale */
u16 cnt;
u16 pwmwidth;
u8 pwmop; /* Output Polarity */
u8 pwmld; /* Immediate Update */
u16 cap; /* Capture internal counter */
u8 ovfpin; /* Ovf and Pin */
u8 intr; /* Interrupts */
} gptmr_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */
u32 cnt; /* 0x08 */
u32 sr; /* 0x0C */
} slt_t;
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_fbctl; /*0x00 */
u8 podr_fbcs; /*0x01 */
u8 podr_dma; /*0x02 */
u8 rsvd1; /*0x03 */
u8 podr_fec0h; /*0x04 */
u8 podr_fec0l; /*0x05 */
u8 podr_fec1h; /*0x06 */
u8 podr_fec1l; /*0x07 */
u8 podr_feci2c; /*0x08 */
u8 podr_pcibg; /*0x09 */
u8 podr_pcibr; /*0x0A */
u8 rsvd2; /*0x0B */
u8 podr_psc3psc2; /*0x0C */
u8 podr_psc1psc0; /*0x0D */
u8 podr_dspi; /*0x0E */
u8 rsvd3; /*0x0F */
/* Port Data Direction Registers */
u8 pddr_fbctl; /*0x10 */
u8 pddr_fbcs; /*0x11 */
u8 pddr_dma; /*0x12 */
u8 rsvd4; /*0x13 */
u8 pddr_fec0h; /*0x14 */
u8 pddr_fec0l; /*0x15 */
u8 pddr_fec1h; /*0x16 */
u8 pddr_fec1l; /*0x17 */
u8 pddr_feci2c; /*0x18 */
u8 pddr_pcibg; /*0x19 */
u8 pddr_pcibr; /*0x1A */
u8 rsvd5; /*0x1B */
u8 pddr_psc3psc2; /*0x1C */
u8 pddr_psc1psc0; /*0x1D */
u8 pddr_dspi; /*0x1E */
u8 rsvd6; /*0x1F */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_fbctl; /*0x20 */
u8 ppdsdr_fbcs; /*0x21 */
u8 ppdsdr_dma; /*0x22 */
u8 rsvd7; /*0x23 */
u8 ppdsdr_fec0h; /*0x24 */
u8 ppdsdr_fec0l; /*0x25 */
u8 ppdsdr_fec1h; /*0x26 */
u8 ppdsdr_fec1l; /*0x27 */
u8 ppdsdr_feci2c; /*0x28 */
u8 ppdsdr_pcibg; /*0x29 */
u8 ppdsdr_pcibr; /*0x2A */
u8 rsvd8; /*0x2B */
u8 ppdsdr_psc3psc2; /*0x2C */
u8 ppdsdr_psc1psc0; /*0x2D */
u8 ppdsdr_dspi; /*0x2E */
u8 rsvd9; /*0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_fbctl; /*0x30 */
u8 pclrr_fbcs; /*0x31 */
u8 pclrr_dma; /*0x32 */
u8 rsvd10; /*0x33 */
u8 pclrr_fec0h; /*0x34 */
u8 pclrr_fec0l; /*0x35 */
u8 pclrr_fec1h; /*0x36 */
u8 pclrr_fec1l; /*0x37 */
u8 pclrr_feci2c; /*0x38 */
u8 pclrr_pcibg; /*0x39 */
u8 pclrr_pcibr; /*0x3A */
u8 rsvd11; /*0x3B */
u8 pclrr_psc3psc2; /*0x3C */
u8 pclrr_psc1psc0; /*0x3D */
u8 pclrr_dspi; /*0x3E */
u8 rsvd12; /*0x3F */
/* Pin Assignment Registers */
u16 par_fbctl; /*0x40 */
u8 par_fbcs; /*0x42 */
u8 par_dma; /*0x43 */
u16 par_feci2cirq; /*0x44 */
u16 rsvd13; /*0x46 */
u16 par_pcibg; /*0x48 */
u16 par_pcibr; /*0x4A */
u8 par_psc3; /*0x4C */
u8 par_psc2; /*0x4D */
u8 par_psc1; /*0x4E */
u8 par_psc0; /*0x4F */
u16 par_dspi; /*0x50 */
u8 par_timer; /*0x52 */
u8 rsvd14; /*0x53 */
} gpio_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id */
u32 scr; /* 0x04 Status / command */
u32 ccrir; /* 0x08 Class Code / Revision Id */
u32 cr1; /* 0x0c Configuration 1 */
u32 bar0; /* 0x10 Base address register 0 */
u32 bar1; /* 0x14 Base address register 1 */
u32 bar2; /* 0x18 NA */
u32 bar3; /* 0x1c NA */
u32 bar4; /* 0x20 NA */
u32 bar5; /* 0x24 NA */
u32 ccpr; /* 0x28 Cardbus CIS Pointer */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
u32 erbar; /* 0x30 Expansion ROM Base Address */
u32 cpr; /* 0x34 Capabilities Pointer */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control */
u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
u32 iw2btar; /* 0x78 NA */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration */
u32 icr; /* 0x84 Initiator Control */
u32 isr; /* 0x88 Initiator Status */
u32 tcr2; /* 0x8c NA */
u32 tbatr0; /* 0x90 NA */
u32 tbatr1; /* 0x94 NA */
u32 tbatr2; /* 0x98 NA */
u32 tbatr3; /* 0x9c NA */
u32 tbatr4; /* 0xa0 NA */
u32 tbatr5; /* 0xa4 NA */
u32 intr; /* 0xa8 NA */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control */
u32 asr; /* Arbiter Status */
};
} pciarb_t;
#endif /* __IMMAP_547x_8x__ */
arch/m68k/include/asm/m547x_8x.h 已删除 100644 → 0
浏览文件 @ 7e58a3a1
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#ifndef mcf547x_8x_h
#define mcf547x_8x_h
/*********************************************************************
* XLB Arbiter (XLB)
*********************************************************************/
/* Bit definitions and macros for XARB_CFG */
#define XARB_CFG_AT (0x00000002)
#define XARB_CFG_DT (0x00000004)
#define XARB_CFG_BA (0x00000008)
#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
#define XARB_CFG_PLDIS (0x80000000)
/* Bit definitions and macros for XARB_SR */
#define XARB_SR_AT (0x00000001)
#define XARB_SR_DT (0x00000002)
#define XARB_SR_BA (0x00000004)
#define XARB_SR_TTM (0x00000008)
#define XARB_SR_ECW (0x00000010)
#define XARB_SR_TTR (0x00000020)
#define XARB_SR_TTA (0x00000040)
#define XARB_SR_MM (0x00000080)
#define XARB_SR_SEA (0x00000100)
/* Bit definitions and macros for XARB_IMR */
#define XARB_IMR_ATE (0x00000001)
#define XARB_IMR_DTE (0x00000002)
#define XARB_IMR_BAE (0x00000004)
#define XARB_IMR_TTME (0x00000008)
#define XARB_IMR_ECWE (0x00000010)
#define XARB_IMR_TTRE (0x00000020)
#define XARB_IMR_TTAE (0x00000040)
#define XARB_IMR_MME (0x00000080)
#define XARB_IMR_SEAE (0x00000100)
/* Bit definitions and macros for XARB_SIGCAP */
#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
#define XARB_SIGCAP_TBST (0x00000020)
#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
/* Bit definitions and macros for XARB_PRIEN */
#define XARB_PRIEN_M0 (0x00000001)
#define XARB_PRIEN_M2 (0x00000004)
#define XARB_PRIEN_M3 (0x00000008)
/* Bit definitions and macros for XARB_PRI */
#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PAR_FBCTL */
#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
#define GPIO_PAR_FBCTL_TA (0x0004)
#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
#define GPIO_PAR_FBCTL_OE (0x0040)
#define GPIO_PAR_FBCTL_BWE0 (0x0100)
#define GPIO_PAR_FBCTL_BWE1 (0x0400)
#define GPIO_PAR_FBCTL_BWE2 (0x1000)
#define GPIO_PAR_FBCTL_BWE3 (0x4000)
#define GPIO_PAR_FBCTL_TS_GPIO (0)
#define GPIO_PAR_FBCTL_TS_TBST (2)
#define GPIO_PAR_FBCTL_TS_TS (3)
#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
/* Bit definitions and macros for GPIO_PAR_FBCS */
#define GPIO_PAR_FBCS_CS1 (0x02)
#define GPIO_PAR_FBCS_CS2 (0x04)
#define GPIO_PAR_FBCS_CS3 (0x08)
#define GPIO_PAR_FBCS_CS4 (0x10)
#define GPIO_PAR_FBCS_CS5 (0x20)
/* Bit definitions and macros for GPIO_PAR_DMA */
#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
#define GPIO_PAR_DMA_DACKx_GPIO (0)
#define GPIO_PAR_DMA_DACKx_TOUT (2)
#define GPIO_PAR_DMA_DACKx_DACK (3)
#define GPIO_PAR_DMA_DREQx_GPIO (0)
#define GPIO_PAR_DMA_DREQx_TIN (2)
#define GPIO_PAR_DMA_DREQx_DREQ (3)
/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
/* Bit definitions and macros for GPIO_PAR_PCIBG */
#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PCIBR */
#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PSC3 */
#define GPIO_PAR_PSC3_TXD3 (0x04)
#define GPIO_PAR_PSC3_RXD3 (0x08)
#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
#define GPIO_PAR_PSC3_RTS3_RTS (0x30)
#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
/* Bit definitions and macros for GPIO_PAR_PSC2 */
#define GPIO_PAR_PSC2_TXD2 (0x04)
#define GPIO_PAR_PSC2_RXD2 (0x08)
#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
#define GPIO_PAR_PSC2_RTS2_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC1 */
#define GPIO_PAR_PSC1_TXD1 (0x04)
#define GPIO_PAR_PSC1_RXD1 (0x08)
#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
#define GPIO_PAR_PSC1_RTS1_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC0 */
#define GPIO_PAR_PSC0_TXD0 (0x04)
#define GPIO_PAR_PSC0_RXD0 (0x08)
#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
#define GPIO_PAR_PSC0_RTS0_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_DSPI */
#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
#define GPIO_PAR_DSPI_CS5 (0x1000)
#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
#define GPIO_PAR_DSPI_CS0_RTS (0x0080)
#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
#define GPIO_PAR_DSPI_SCK_CTS (0x0020)
#define GPIO_PAR_DSPI_SCK_SCK (0x0030)
#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
#define GPIO_PAR_DSPI_SIN_RXD (0x0008)
#define GPIO_PAR_DSPI_SIN_SIN (0x000C)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
/* Bit definitions and macros for GPIO_PAR_TIMER */
#define GPIO_PAR_TIMER_TOUT2 (0x01)
#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
#define GPIO_PAR_TIMER_TOUT3 (0x08)
#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
#define GPIO_PAR_TIMER_TIN3_TIN (0x30)
#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
#define GPIO_PAR_TIMER_TIN2_TIN (0x06)
/*********************************************************************
* Slice Timer (SLT)
*********************************************************************/
#define SLT_CR_RUN (0x04000000)
#define SLT_CR_IEN (0x02000000)
#define SLT_CR_TEN (0x01000000)
#define SLT_SR_BE (0x02000000)
#define SLT_SR_ST (0x01000000)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EP0ISR (15)
#define INT0_LO_EP1ISR (16)
#define INT0_LO_EP2ISR (17)
#define INT0_LO_EP3ISR (18)
#define INT0_LO_EP4ISR (19)
#define INT0_LO_EP5ISR (20)
#define INT0_LO_EP6ISR (21)
#define INT0_LO_USBISR (22)
#define INT0_LO_USBAISR (23)
#define INT0_LO_USB (24)
#define INT1_LO_DSPI_RFOF_TFUF (25)
#define INT1_LO_DSPI_RFOF (26)
#define INT1_LO_DSPI_RFDF (27)
#define INT1_LO_DSPI_TFUF (28)
#define INT1_LO_DSPI_TCF (29)
#define INT1_LO_DSPI_TFFF (30)
#define INT1_LO_DSPI_EOQF (31)
#define INT0_HI_UART3 (32)
#define INT0_HI_UART2 (33)
#define INT0_HI_UART1 (34)
#define INT0_HI_UART0 (35)
#define INT0_HI_COMMTIM_TC (36)
#define INT0_HI_SEC (37)
#define INT0_HI_FEC1 (38)
#define INT0_HI_FEC0 (39)
#define INT0_HI_I2C (40)
#define INT0_HI_PCIARB (41)
#define INT0_HI_CBPCI (42)
#define INT0_HI_XLBPCI (43)
#define INT0_HI_XLBARB (47)
#define INT0_HI_DMA (48)
#define INT0_HI_CAN0_ERROR (49)
#define INT0_HI_CAN0_BUSOFF (50)
#define INT0_HI_CAN0_MBOR (51)
#define INT0_HI_SLT1 (53)
#define INT0_HI_SLT0 (54)
#define INT0_HI_CAN1_ERROR (55)
#define INT0_HI_CAN1_BUSOFF (56)
#define INT0_HI_CAN1_MBOR (57)
#define INT0_HI_GPT3 (59)
#define INT0_HI_GPT2 (60)
#define INT0_HI_GPT1 (61)
#define INT0_HI_GPT0 (62)
/*********************************************************************
* General Purpose Timers (GPTMR)
*********************************************************************/
/* Enable and Mode Select */
#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
#define GPT_CTRL_CE 0x10 /* Counter Enable */
#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
#define GPT_PWM_WIDTH(x) (x & 0xffff)
/* Status */
#define GPT_STA_CAPTURE(x) (x & 0xffff)
#define GPT_OVFPIN_OVF(x) (x & 0x70)
#define GPT_OVFPIN_PIN 0x01
#define GPT_INT_TEXP 0x08
#define GPT_INT_PWMP 0x04
#define GPT_INT_COMP 0x02
#define GPT_INT_CAPT 0x01
/*********************************************************************
* PCI
*********************************************************************/
/* Bit definitions and macros for SCR */
#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
#define PCI_SCR_SE (0x40000000) /* System error signalled */
#define PCI_SCR_MA (0x20000000) /* Master aboart received */
#define PCI_SCR_TR (0x10000000) /* Target abort received */
#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
#define PCI_SCR_DP (0x01000000) /* Master data parity err */
#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
#define PCI_SCR_R (0x00400000) /* Reserved */
#define PCI_SCR_66M (0x00200000) /* 66Mhz */
#define PCI_SCR_C (0x00100000) /* Capabilities list */
#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
#define PCI_SCR_S (0x00000100) /* SERR enable */
#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
#define PCI_SCR_PER (0x00000040) /* Parity error response */
#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
#define PCI_SCR_B (0x00000004) /* Bus master enable */
#define PCI_SCR_M (0x00000002) /* Memory access control */
#define PCI_SCR_IO (0x00000001) /* I/O access control */
#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
#define PCI_BAR_BAR1(x) (x & 0xC0000000)
#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
#define PCI_GSCR_SE (0x10000000) /* SERR detected */
#define PCI_GSCR_ER (0x08000000) /* Error response detected */
#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
#define PCI_GSCR_PR (0x00000001) /* PCI reset */
#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
#define PCI_TCR1_B5E (0x00002000) /* */
#define PCI_TCR1_B4E (0x00001000) /* */
#define PCI_TCR1_B3E (0x00000800) /* */
#define PCI_TCR1_B2E (0x00000400) /* */
#define PCI_TCR1_B1E (0x00000200) /* */
#define PCI_TCR1_B0E (0x00000100) /* */
#define PCI_TCR1_CR (0x00000001) /* */
#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
#define PCI_TBATR_EN (0x00000001) /* Enable */
#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
#define PCIARB_ACR_DS (0x80000000)
#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
#define PCIARB_ARC_INTMINTEN (0x00010000)
#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
#define PCIARB_ARC_INTMPRI (0x00000001)
#endif /* mcf547x_8x_h */
arch/m68k/lib/cache.c
浏览文件 @ bfb5bfa3
......@@ -80,7 +80,7 @@ void icache_invalid(void)
}
/*
* data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
* data cache only for ColdFire V4 such as MCF5445x
* the dcache will be dummy in ColdFire V2 and V3
*/
void dcache_enable(void)
......
arch/powerpc/Kconfig
浏览文件 @ bfb5bfa3
......@@ -25,12 +25,6 @@ config MPC85xx
imply CMD_IRQ
imply USB_EHCI_HCD if USB
config MPC86xx
bool "MPC86xx"
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
imply CMD_REGINFO
config MPC8xx
bool "MPC8xx"
select BOARD_EARLY_INIT_F
......@@ -47,7 +41,6 @@ config HIGH_BATS
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
source "arch/powerpc/lib/Kconfig"
......
arch/powerpc/cpu/mpc83xx/Kconfig
浏览文件 @ bfb5bfa3
......@@ -8,52 +8,6 @@ choice
prompt "Target select"
optional
config TARGET_MPC8308_P1M
bool "Support mpc8308_p1m"
select ARCH_MPC8308
config TARGET_SBC8349
bool "Support sbc8349"
select ARCH_MPC8349
config TARGET_VE8313
bool "Support ve8313"
select ARCH_MPC8313
config TARGET_VME8349
bool "Support vme8349"
select ARCH_MPC8349
config TARGET_CADDY2
bool "Support caddy2"
select ARCH_MPC8349
config TARGET_MPC8313ERDB_NOR
bool "Support MPC8313ERDB_NOR"
select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_MPC8313ERDB_NAND
bool "Support MPC8313ERDB_NAND"
select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
select ARCH_MPC8315
select BOARD_EARLY_INIT_F
config TARGET_MPC8323ERDB
bool "Support MPC8323ERDB"
select ARCH_MPC832X
config TARGET_MPC832XEMDS
bool "Support MPC832XEMDS"
select ARCH_MPC832X
select BOARD_EARLY_INIT_F
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
select ARCH_MPC8349
......@@ -121,11 +75,6 @@ config TARGET_KMTEPR2
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TQM834X
bool "Support TQM834x"
select ARCH_MPC8349
config TARGET_GAZERBEAM
bool "Support gazerbeam"
select ARCH_MPC8308
......@@ -212,14 +161,6 @@ config ARCH_MPC8313
select MPC83XX_SECOND_I2C_SUPPORT
select FSL_ELBC
config ARCH_MPC8315
bool
select ARCH_MPC831X
select MPC83XX_PCIE1_SUPPORT
select MPC83XX_PCIE2_SUPPORT
select MPC83XX_SATA_SUPPORT
select FSL_ELBC
config ARCH_MPC832X
bool
select MPC83XX_QUICC_ENGINE
......@@ -302,19 +243,10 @@ endmenu
config FSL_ELBC
bool
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
source "board/mpc8308_p1m/Kconfig"
source "board/sbc8349/Kconfig"
source "board/tqc/tqm834x/Kconfig"
source "board/ve8313/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
endmenu
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
浏览文件 @ bfb5bfa3
......@@ -19,7 +19,7 @@ config DDR_MC_CLOCK_MODE_1_2
bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1
depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
bool "1 : 1"
endchoice
......@@ -143,7 +143,6 @@ config CORE_PLL_VCO_DIVIDER_4
bool "4"
config CORE_PLL_VCO_DIVIDER_8
depends on !ARCH_MPC8315
bool "8"
endchoice
......
arch/powerpc/cpu/mpc83xx/speed.c
浏览文件 @ bfb5bfa3
......@@ -104,9 +104,6 @@ int get_clocks(void)
#if !defined(CONFIG_ARCH_MPC832X)
u32 i2c2_clk;
#endif
#if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
......@@ -130,7 +127,7 @@ int get_clocks(void)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
#if defined(CONFIG_ARCH_MPC837X)
u32 sata_clk;
#endif
......@@ -200,8 +197,8 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
......@@ -294,25 +291,6 @@ int get_clocks(void)
return -8;
}
#endif
#if defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
break;
case 1:
tdm_clk = csb_clk;
break;
case 2:
tdm_clk = csb_clk / 2;
break;
case 3:
tdm_clk = csb_clk / 3;
break;
default:
/* unknown SCCR_TDMCM value */
return -8;
}
#endif
#if defined(CONFIG_ARCH_MPC834X)
i2c1_clk = tsec2_clk;
......@@ -372,7 +350,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
#if defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
......@@ -462,9 +440,6 @@ int get_clocks(void)
#if defined(CONFIG_ARCH_MPC834X)
gd->arch.usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_ARCH_MPC8315)
gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = sdhc_clk;
#endif
......@@ -491,7 +466,7 @@ int get_clocks(void)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
#if defined(CONFIG_ARCH_MPC837X)
gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
......@@ -559,10 +534,6 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" I2C2: %-4s MHz\n",
strmhz(buf, gd->arch.i2c2_clk));
#endif
#if defined(CONFIG_ARCH_MPC8315)
printf(" TDM: %-4s MHz\n",
strmhz(buf, gd->arch.tdm_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
......@@ -590,7 +561,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
#endif
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
#if defined(CONFIG_ARCH_MPC837X)
printf(" SATA: %-4s MHz\n",
strmhz(buf, gd->arch.sata_clk));
#endif
......
arch/powerpc/cpu/mpc85xx/Kconfig
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......@@ -301,8 +301,7 @@ int checkcpu (void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
......
arch/powerpc/cpu/mpc85xx/fdt.c
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......@@ -392,7 +392,7 @@ const char *serdes_clock_to_string(u32 clock)
case SRDS_PLLCR0_RFCK_SEL_161_13:
return "161.1328123";
default:
#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
#if defined(CONFIG_TARGET_T4240QDS)
return "???";
#else
return "122.88";
......
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2004 Freescale Semiconductor.
# Jeff Brown
PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float
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board/xes/common/Makefile
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cmd/Kconfig
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configs/P1010RDB-PA_NAND_defconfig
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configs/P1010RDB-PA_NOR_defconfig
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configs/P1010RDB-PB_NAND_defconfig
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configs/P1010RDB-PB_NOR_defconfig
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configs/P1020RDB-PC_36BIT_defconfig
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configs/P1020RDB-PC_NAND_defconfig
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configs/P1020RDB-PC_defconfig
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configs/P1020RDB-PD_NAND_defconfig
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configs/P1020RDB-PD_defconfig
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configs/P2020RDB-PC_36BIT_defconfig
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configs/P2020RDB-PC_NAND_defconfig
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configs/P2020RDB-PC_defconfig
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configs/P2041RDB_NAND_defconfig
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configs/P2041RDB_SDCARD_defconfig
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configs/P2041RDB_SPIFLASH_defconfig
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configs/P2041RDB_defconfig
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configs/T1024RDB_NAND_defconfig
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configs/T1024RDB_SDCARD_defconfig
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configs/T1024RDB_SPIFLASH_defconfig
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configs/T1024RDB_defconfig
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include/configs/xpedite550x.h 已删除 100644 → 0
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include/fsl_dspi.h
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include/mpc83xx.h
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include/pci.h
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include/post.h
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