- 16 7月, 2010 16 次提交
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由 Kumar Gala 提交于
Add 'errata' command to report what errata we workaround. Report workaround for erratum SATA-A001 on P1022/P1013. Also sorted the CONFIG_CMD_* list. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that we can capture the LAW target for a given PCI or PCIE controller. Also update the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure. This will allow future PCI[E] code to configure the LAW target automatically, rather than requiring each board to it for each PCI controller separately. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
The e5500 has a link register stack and segment target address cache. Its safe to enable these bits on older e500 cores as the bits are implemented in the register. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Acked-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
The new command dumps the TLBCAM, the LAWs, and the BR/OR regs. Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
This dumps out the contents of TLB1 on 85xx-based systems. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
Extract the operation to read a tlb into a function - we will need this later to print out the tlbs, and there's no point in duplicating the code. Create a TSIZE_TO_BYTES macro to deal with the conversion from the MAS field to an actual size instead of duplicating this in code. There are a few misc other minor cleanups. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Acked-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
If we explicitly disabled a core remove it from the dtb we pass on to the kernel. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We may have cpu-handles pointing to the cpu nodes we delete. If so we should delete the handles as well. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kim Phillips 提交于
Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kim Phillips 提交于
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x. Parts with newer SEC h/w versions will increment the number to accomodate incompatible code changes. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kim Phillips 提交于
Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 7月, 2010 1 次提交
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由 Ilya Yanok 提交于
This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch). Signed-off-by: NIlya Yanok <yanok@emcraft.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 05 7月, 2010 1 次提交
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由 Wolfgang Denk 提交于
The hush shell dynamically allocates (and re-allocates) memory for the argument strings in the "char *argv[]" argument vector passed to commands. Any code that modifies these pointers will cause serious corruption of the malloc data structures and crash U-Boot, so make sure the compiler can check that no such modifications are being done by changing the code into "char * const argv[]". This modification is the result of debugging a strange crash caused after adding a new command, which used the following argument processing code which has been working perfectly fine in all Unix systems since version 6 - but not so in U-Boot: int main (int argc, char **argv) { while (--argc > 0 && **++argv == '-') { /* ====> */ while (*++*argv) { switch (**argv) { case 'd': debug++; break; ... default: usage (); } } } ... } The line marked "====>" will corrupt the malloc data structures and usually cause U-Boot to crash when the next command gets executed by the shell. With the modification, the compiler will prevent this with an error: increment of read-only location '*argv' N.B.: The code above can be trivially rewritten like this: while (--argc > 0 && **++argv == '-') { char *arg = *argv; while (*++arg) { switch (*arg) { ... Signed-off-by: NWolfgang Denk <wd@denx.de> Acked-by: NMike Frysinger <vapier@gentoo.org>
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- 01 7月, 2010 6 次提交
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由 Stefan Roese 提交于
Background Info: Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via init.S) to speed up the boot process. In relocate_code (start.S) the cache inhibit attribute for this TLB is set to disable cache. This is needed for the CFI FLASH driver. This patch now cleans this code up: - CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not defined in the top of this file. This way, we can remove an ugly #ifdef in this code. - Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..." statement with "#if defined(CONFIG_440)". - Remove unnecessary cache invalidate calls resulting in faster bootup. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds some DDR(2) macros to all PPC4xx's equipped with this IBM DDR1/2 controller. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
As described in item #10 of the SDRAM initialization (chapter 22.2.9 of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The code for this is now factored out and executed for non-SPD based boards as well. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch makes it possible to overwrite the default auto-calibration scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with board specific values. The parameters of the weak default function are corrected as well. This way we don't need the casts any more. This feature will be used by an upcoming PPC460GT board port. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
By not defining CONFIG_SYS_PCI_MASTER_INIT and CONFIG_SYS_PCI_TARGET_INIT, PCI support (host and adapter) will not be enabled. But it's still possible to use the U-Boot PCI infrastructure for the PCIe ports. This configuration option is needed for a new 460GT board, which uses PCIe but has PCI disabled. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch enables booting with option E on the PPC460EX/EXr/GT. When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0. The Software Boot Configuration Procedure is needed to engage the PLL and perform a chip reset. Signed-off-by: NStefan Roese <sr@denx.de>
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- 30 6月, 2010 1 次提交
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由 Michael Weiss 提交于
This also uses the breadcrumb register as on MPC5200. Signed-off-by: NMichael Weiss <michael.weiss@ifm.com> Signed-off-by: NDetlev Zundel <dzu@denx.de>
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- 29 6月, 2010 1 次提交
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由 Wolfgang Denk 提交于
Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned local bus accesses" fixed the problem for MPC5200 only, but MPC512x is affected as well, so apply the same fix here, too. Signed-off-by: NWolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: NDetlev Zundel <dzu@denx.de>
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- 24 6月, 2010 2 次提交
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由 Wolfgang Denk 提交于
The AmigaOneG3SE board has been orphaned or a very long time, and broken for more than 12 releases resp. more than 3 years. As nobody seems to be interested any more in this stuff we may as well ged rid of it, especially as it clutters many areas of the code so it is a continuous pain for all kinds of ongoing work. Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
CONFIG_SYS_BUS_HZ has not really been used anywhere except to be redined as CONFIG_SYS_BUS_CLK; in addition, the mpc7448hpc2 had the bogus CONFIG_SYS_CONFIG_BUS_CLK setting which duplicated the funtionality. Change all this to use CONFIG_SYS_BUS_CLK consistently. Signed-off-by: NWolfgang Denk <wd@denx.de> Cc: Frank Gottschling <fgottschling@eltec.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Eran Man <eran@nbase.co.il> Cc: Stefan Roese <sr@denx.de> Cc: Nye Liu <nyet@zumanetworks.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
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- 23 6月, 2010 1 次提交
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由 Wolfgang Denk 提交于
The MPC5200 has a nasty problem that will cause silent data corruption when performing unaligned 16 or 32 byte accesses when reading from the local bus - typically this affects reading from flash. The problem can be easily shown: => md fc0c0000 10 fc0c0000: 323e4337 01626f6f 74636d64 3d72756e 2>C7.bootcmd=run fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel fc0c0020: 61793d35 00626175 64726174 653d3131 ay=5.baudrate=11 fc0c0030: 35323030 00707265 626f6f74 3d656368 5200.preboot=ech => md fc0c0001 10 fc0c0001: 65636801 00000074 0000003d 00000020 ech....t...=... fc0c0011: 0000005f 00000000 00000074 00000061 ..._.......t...a fc0c0021: 00000000 00000064 00000065 00000035 .......d...e...5 fc0c0031: 00000000 00000062 0000003d 0000006f .......b...=...o => md.w fc0c0001 10 fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20 ..7...ot..d=..n fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61 ..t_..s...ot..la This commit implements a workaround at least for the most blatant problem: using memcpy() from NOR flash. We rename the assembler routine into __memcpy() and provide a wrapper, which will use a byte-wise copy loop for unaligned source or target addresses when reading from NOR flash, and branch to the optimized __memcpy() in all other cases, thus minimizing the performance impact. Tested on lite5200b and TQM5200S. Signed-off-by: NWolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
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- 14 6月, 2010 1 次提交
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由 Anatolij Gustschin 提交于
Do not enforce drivers to provide empty video_set_lut() if they do not implement indexed color (8 bpp) frame buffer support. Add default function to the cfb_console driver and remove empty video_set_lut() functions. Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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- 31 5月, 2010 1 次提交
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由 Timur Tabi 提交于
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 27 5月, 2010 2 次提交
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由 Kumar Gala 提交于
Match style we use almost everywhere else Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Michael Weiss 提交于
For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem. Signed-off-by: NMichael Weiss <michael.weiss@ifm.com> Signed-off-by: NDetlev Zundel <dzu@denx.de>
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- 22 5月, 2010 2 次提交
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由 Kim Phillips 提交于
commit c7190f02 "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Horst Kronstorfer 提交于
Signed-off-by: NHorst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 18 5月, 2010 1 次提交
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由 Kim Phillips 提交于
commit 167cdad1 "SERIAL: Enable port-mapped access" inadvertently broke 83xx nand boards by converting NS16550_init to use io accessors, which expanded the size of the generated code. this patch fixes the problem by removing icache functions from the nand builds, which somewhat follows commit 1a2e203b "mpc83xx: turn on icache in core initialization to improve u-boot boot time" Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 12 5月, 2010 4 次提交
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由 York Sun 提交于
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. The difference has ben examined and the code is compatible. Speed bins is not verified on hardware for CL7 at this moment. This patch also enables SPD Rev 1.x where x is up to "F". According to SPD spec, the lower nibble is optionally used to determine which additinal bytes or attribute bits have been defined. Software can safely use defaults. However, the upper nibble should always be checked. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code. Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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