Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Add dmc and phy_control register structure for 5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Add structure for power register for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adding Maintainer for AM43xx.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: NTom Rini <trini@ti.com>

Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Current Booting devices list is different from that of AM33xx.
Updating the same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Selecting the Master osc clk as Timer2 clock source.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Add Extra env settings.
This is derived from am335x Extra ENV settings.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

AM4372 uses PL310 L2 Cache. Enable the configs for the same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Use ti_armv7_common.h config file to inclde the common
configs.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>

The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across
U-Boot. Fix this.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swrren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Create the i2c adapter object for the fifth bus on SoC with more than
4 buses. This allow using all the bus available on T30.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>
Acked-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: NJulian Scheel <julian.scheel@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Fix the timeout issue after running "bootp" command in u-boot
console. For example you see "EHCI timed out on TD- token=0x...".
TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10
after a controller reset and before RUN bit is set
(per technical reference manual).
Signed-off-by: NJim Lin <jilin@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

u-boot-dtb-tegra.bin and u-boot-nodtb-tegra.bin binaries
are generated only if the SPL build is enabled as they have
dependency on SPL build
Signed-off-by: NVidya Sagar <vidyas@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

I no longer work for Avionic Design and don't have access to hardware,
so I'll pass on maintainership to Alban.
Acked-by: NAlban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.
Signed-off-by: NJimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: NTom Warren <twarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

When DT define aliases for etherner0 and ethernet1, U-Boot
automatically patched MAC addresses using ethaddr and eth1addr
environment variables respectively.

Custom initialization is no longer needed.
Signed-off-by: NSergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>

DT kernel requires CONFIG_OF_LIBFDT. 'bootm' needs to know DT location.
In addition, fix kernel console device and enable U-Boot long help.
Signed-off-by: NSergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>

Initial configuration has worng address of the second chip.
There is an alias for the 1st chip at 0x02000000 in earlier
verions of LP-8x4x, so the boot normally.

However, new LP-8x4xs have a bigger 1st flash chip, and hang on
boot without this patch.
Signed-off-by: NSergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>