arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de> Acked-by: NStephen Warren <swarren@nvidia.com> Tested-by: NStephen Warren <swrren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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