Exynos5420: Add clock initialization for 5420

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

arch/arm/cpu/armv7/exynos/clock.c

@@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 
 	freq = CONFIG_SYS_CLK_FREQ;
 
-	if (pllreg == EPLL) {
+	if (pllreg == EPLL || pllreg == RPLL) {
 		k = k & 0xffff;
 		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
 		fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
@@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 			div = PLL_DIV_1024;
 		else if (proid_is_exynos4412())
 			div = PLL_DIV_65535;
-		else if (proid_is_exynos5250())
+		else if (proid_is_exynos5250() || proid_is_exynos5420())
 			div = PLL_DIV_65536;
 		else
 			return 0;
@@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
 		return 0;
 }
 
+/* exynos5420: return pll clock frequency */
+static unsigned long exynos5420_get_pll_clk(int pllreg)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
+	case RPLL:
+		r = readl(&clk->rpll_con0);
+		k = readl(&clk->rpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos4: return ARM clock frequency */
 static unsigned long exynos4_get_arm_clk(void)
 {
@@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
 	return pclk;
 }
 
+/* exynos5420: return pwm clock frequency */
+static unsigned long exynos5420_get_pwm_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int ratio;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * PWM_RATIO [31:28]
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> 28) & 0xf;
+	sclk = get_pll_clk(MPLL);
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 /* exynos4: return uart clock frequency */
 static unsigned long exynos4_get_uart_clk(int dev_index)
 {
@@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
 	return uclk;
 }
 
+/* exynos5420: return uart clock frequency */
+static unsigned long exynos5420_get_uart_clk(int dev_index)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIC0
+	 * UART0_SEL [6:4]
+	 * UART1_SEL [10:8]
+	 * UART2_SEL [14:12]
+	 * UART3_SEL [18:16]
+	 * generalised calculation as follows
+	 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
+	 */
+	sel = readl(&clk->src_peric0);
+	sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
+
+	if (sel == 0x3)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x6)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(RPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * UART0_RATIO [11:8]
+	 * UART1_RATIO [15:12]
+	 * UART2_RATIO [19:16]
+	 * UART3_RATIO [23:20]
+	 * generalised calculation as follows
+	 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
 static unsigned long exynos4_get_mmc_clk(int dev_index)
 {
 	struct exynos4_clock *clk =
@@ -718,6 +823,47 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
 	return uclk;
 }
 
+static unsigned long exynos5420_get_mmc_clk(int dev_index)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio;
+
+	/*
+	 * CLK_SRC_FSYS
+	 * MMC0_SEL [10:8]
+	 * MMC1_SEL [14:12]
+	 * MMC2_SEL [18:16]
+	 * generalised calculation as follows
+	 * sel = (sel >> ((dev_index * 4) + 8)) & mask
+	 */
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
+
+	if (sel == 0x3)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x6)
+		sclk = get_pll_clk(EPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_RATIO [9:0]
+	 * MMC1_RATIO [19:10]
+	 * MMC2_RATIO [29:20]
+	 * generalised calculation as follows
+	 * ratio = (ratio >> (dev_index * 10)) & mask
+	 */
+	ratio = readl(&clk->div_fsys1);
+	ratio = (ratio >> (dev_index * 10)) & 0x3ff;
+
+	uclk = (sclk / (ratio + 1));
+
+	return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -804,6 +950,29 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	writel(val, addr);
 }
 
+/* exynos5: set the mmc clock */
+static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int addr;
+	unsigned int val, shift;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_RATIO [9:0]
+	 * MMC1_RATIO [19:10]
+	 * MMC2_RATIO [29:20]
+	 */
+	addr = (unsigned int)&clk->div_fsys1;
+	shift = dev_index * 10;
+
+	val = readl(addr);
+	val &= ~(0x3ff << shift);
+	val |= (div & 0x3ff) << shift;
+	writel(val, addr);
+}
+
 /* get_lcd_clk: return lcd clock frequency */
 static unsigned long exynos4_get_lcd_clk(void)
 {
@@ -1324,6 +1493,71 @@ static int exynos5_set_spi_clk(enum periph_id periph_id,
 	return 0;
 }
 
+static int exynos5420_set_spi_clk(enum periph_id periph_id,
+					unsigned int rate)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	int main;
+	unsigned int fine;
+	unsigned shift, pre_shift;
+	unsigned div_mask = 0xf, pre_div_mask = 0xff;
+	u32 *reg;
+	u32 *pre_reg;
+
+	main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+	if (main < 0) {
+		debug("%s: Cannot set clock rate for periph %d",
+		      __func__, periph_id);
+		return -1;
+	}
+	main = main - 1;
+	fine = fine - 1;
+
+	switch (periph_id) {
+	case PERIPH_ID_SPI0:
+		reg = &clk->div_peric1;
+		shift = 20;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 8;
+		break;
+	case PERIPH_ID_SPI1:
+		reg = &clk->div_peric1;
+		shift = 24;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 16;
+		break;
+	case PERIPH_ID_SPI2:
+		reg = &clk->div_peric1;
+		shift = 28;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 24;
+		break;
+	case PERIPH_ID_SPI3:
+		reg = &clk->div_isp1;
+		shift = 16;
+		pre_reg = &clk->div_isp1;
+		pre_shift = 0;
+		break;
+	case PERIPH_ID_SPI4:
+		reg = &clk->div_isp1;
+		shift = 20;
+		pre_reg = &clk->div_isp1;
+		pre_shift = 8;
+		break;
+	default:
+		debug("%s: Unsupported peripheral ID %d\n", __func__,
+		      periph_id);
+		return -1;
+	}
+
+	clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
+	clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
+			(fine & pre_div_mask) << pre_shift);
+
+	return 0;
+}
+
 static unsigned long exynos4_get_i2c_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1341,9 +1575,11 @@ static unsigned long exynos4_get_i2c_clk(void)
 
 unsigned long get_pll_clk(int pllreg)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
-	else {
+	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_pll_clk(pllreg);
 		return exynos4_get_pll_clk(pllreg);
@@ -1375,9 +1611,11 @@ unsigned long get_i2c_clk(void)
 
 unsigned long get_pwm_clk(void)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_pwm_clk();
 		return clock_get_periph_rate(PERIPH_ID_PWM0);
-	else {
+	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_pwm_clk();
 		return exynos4_get_pwm_clk();
@@ -1386,9 +1624,11 @@ unsigned long get_pwm_clk(void)
 
 unsigned long get_uart_clk(int dev_index)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_uart_clk(dev_index);
 		return exynos5_get_uart_clk(dev_index);
-	else {
+	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_uart_clk(dev_index);
 		return exynos4_get_uart_clk(dev_index);
@@ -1397,17 +1637,23 @@ unsigned long get_uart_clk(int dev_index)
 
 unsigned long get_mmc_clk(int dev_index)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_mmc_clk(dev_index);
 		return exynos5_get_mmc_clk(dev_index);
-	else
+	} else {
 		return exynos4_get_mmc_clk(dev_index);
+	}
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-	if (cpu_is_exynos5())
-		exynos5_set_mmc_clk(dev_index, div);
-	else {
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			exynos5420_set_mmc_clk(dev_index, div);
+		else
+			exynos5_set_mmc_clk(dev_index, div);
+	} else {
 		if (proid_is_exynos4412())
 			exynos4x12_set_mmc_clk(dev_index, div);
 		else
@@ -1439,10 +1685,13 @@ void set_mipi_clk(void)
 
 int set_spi_clk(int periph_id, unsigned int rate)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_set_spi_clk(periph_id, rate);
 		return exynos5_set_spi_clk(periph_id, rate);
-	else
+	} else {
 		return 0;
+	}
 }
 
 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,

arch/arm/cpu/armv7/exynos/clock_init.h

@@ -10,7 +10,11 @@
 #define __EXYNOS_CLOCK_INIT_H
 
 enum {
+#ifdef CONFIG_EXYNOS5420
+	MEM_TIMINGS_MSR_COUNT	= 5,
+#else
 	MEM_TIMINGS_MSR_COUNT	= 4,
+#endif
 };
 
 /* These are the ratio's for configuring ARM clock */
@@ -59,6 +63,18 @@ struct mem_timings {
 	unsigned bpll_mdiv;
 	unsigned bpll_pdiv;
 	unsigned bpll_sdiv;
+	unsigned kpll_mdiv;
+	unsigned kpll_pdiv;
+	unsigned kpll_sdiv;
+	unsigned dpll_mdiv;
+	unsigned dpll_pdiv;
+	unsigned dpll_sdiv;
+	unsigned ipll_mdiv;
+	unsigned ipll_pdiv;
+	unsigned ipll_sdiv;
+	unsigned spll_mdiv;
+	unsigned spll_pdiv;
+	unsigned spll_sdiv;
 	unsigned pclk_cdrex_ratio;
 	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
 
@@ -115,6 +131,7 @@ struct mem_timings {
 	uint8_t send_zq_init;		/* 1 to send this command */
 	unsigned impedance;		/* drive strength impedeance */
 	uint8_t gate_leveling_enable;	/* check gate leveling is enabled */
+	uint8_t read_leveling_enable;	/* check h/w read leveling is enabled */
 };
 
 /**

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c

@@ -24,6 +24,24 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct arm_clk_ratios arm_clk_ratios[] = {
+#ifdef CONFIG_EXYNOS5420
+	{
+		.arm_freq_mhz = 900,
+
+		.apll_mdiv = 0x96,
+		.apll_pdiv = 0x2,
+		.apll_sdiv = 0x1,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x6,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x0,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}
+#else
 	{
 		.arm_freq_mhz = 600,
 
@@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = {
 		.cpud_ratio = 0x3,
 		.arm_ratio = 0x0,
 	}
+#endif
 };
+
 struct mem_timings mem_timings[] = {
+#ifdef CONFIG_EXYNOS5420
+	{
+		.mem_manuf = MEM_MANUF_SAMSUNG,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+
+		/* MPLL @800MHz*/
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x1,
+		/* CPLL @666MHz */
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x1,
+		/* EPLL @600MHz */
+		.epll_mdiv = 0x64,
+		.epll_pdiv = 0x2,
+		.epll_sdiv = 0x1,
+		/* VPLL @430MHz */
+		.vpll_mdiv = 0xd7,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+		/* BPLL @800MHz */
+		.bpll_mdiv = 0xc8,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x1,
+		/* KPLL @600MHz */
+		.kpll_mdiv = 0x190,
+		.kpll_pdiv = 0x4,
+		.kpll_sdiv = 0x2,
+		/* DPLL @600MHz */
+		.dpll_mdiv = 0x190,
+		.dpll_pdiv = 0x4,
+		.dpll_sdiv = 0x2,
+		/* IPLL @370MHz */
+		.ipll_mdiv = 0xb9,
+		.ipll_pdiv = 0x3,
+		.ipll_sdiv = 0x2,
+		/* SPLL @400MHz */
+		.spll_mdiv = 0xc8,
+		.spll_pdiv = 0x3,
+		.spll_sdiv = 0x2,
+
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
+			0x00000c70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x6836650f,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a26,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x8,
+		.phy1_tFS = 0x8,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x7,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 1,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_DISABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 1,
+		.chips_per_channel = 1,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.gate_leveling_enable = 1,
+		.read_leveling_enable = 0,
+	}
+#else
 	{
 		.mem_manuf = MEM_MANUF_ELPIDA,
 		.mem_type = DDR_MODE_DDR3,
@@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = {
 		.impedance = IMP_OUTPUT_DRV_40_OHM,
 		.gate_leveling_enable = 1,
 	}
+#endif
 };
 
 /**
@@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void)
 	return NULL;
 }
 
-void system_clock_init()
+static void exynos5250_system_clock_init(void)
 {
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
@@ -436,19 +580,13 @@ void system_clock_init()
 	} while ((val | MUX_BPLL_SEL_MASK) != val);
 
 	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &clk->apll_lock);
-
-	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-
-	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-
-	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-
-	writel(GPLL_LOCK_VAL, &clk->gpll_lock);
-
-	writel(EPLL_LOCK_VAL, &clk->epll_lock);
-
-	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+	writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+	writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
+	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+	writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
 
 	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
 
@@ -640,6 +778,192 @@ void system_clock_init()
 	writel(val, &clk->div_fsys2);
 }
 
+static void exynos5420_system_clock_init(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct mem_timings *mem;
+	struct arm_clk_ratios *arm_clk_ratio;
+	u32 val;
+
+	mem = clock_get_mem_timings();
+	arm_clk_ratio = get_arm_ratios();
+
+	/* PLL locktime */
+	writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+	writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
+	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+	writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
+	writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
+	writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
+	writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+
+	setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
+
+	writel(0, &clk->src_top6);
+
+	writel(0, &clk->src_cdrex);
+	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+	writel(HPM_RATIO,  &clk->div_cpu1);
+	writel(CLK_DIV_CPU0_VAL,  &clk->div_cpu0);
+
+	/* switch A15 clock source to OSC clock before changing APLL */
+	clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	val = set_pll(arm_clk_ratio->apll_mdiv,
+		      arm_clk_ratio->apll_pdiv,
+		      arm_clk_ratio->apll_sdiv);
+	writel(val, &clk->apll_con0);
+	while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* now it is safe to switch to APLL */
+	setbits_le32(&clk->src_cpu, APLL_FOUT);
+
+	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+	writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
+
+	/* switch A7 clock source to OSC clock before changing KPLL */
+	clrbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+	/* Set KPLL*/
+	writel(KPLL_CON1_VAL, &clk->kpll_con1);
+	val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
+	writel(val, &clk->kpll_con0);
+	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* now it is safe to switch to KPLL */
+	setbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+	writel(val, &clk->mpll_con0);
+	while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set DPLL */
+	writel(DPLL_CON1_VAL, &clk->dpll_con1);
+	val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
+	writel(val, &clk->dpll_con0);
+	while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+	writel(val, &clk->epll_con0);
+	while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+	writel(val, &clk->cpll_con0);
+	while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set IPLL */
+	writel(IPLL_CON1_VAL, &clk->ipll_con1);
+	val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
+	writel(val, &clk->ipll_con0);
+	while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set VPLL */
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+	writel(val, &clk->vpll_con0);
+	while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set BPLL */
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+	writel(val, &clk->bpll_con0);
+	while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set SPLL */
+	writel(SPLL_CON1_VAL, &clk->spll_con1);
+	val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
+	writel(val, &clk->spll_con0);
+	while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+		;
+
+	writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
+	writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+	writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
+
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
+
+	writel(0, &clk->src_top10);
+	writel(0, &clk->src_top11);
+	writel(0, &clk->src_top12);
+
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+	writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
+	writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
+
+	/* DISP1 BLK CLK SELECTION */
+	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
+	writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
+
+	/* AUDIO BLK */
+	writel(AUDIO0_SEL_EPLL, &clk->src_mau);
+	writel(DIV_MAU_VAL, &clk->div_mau);
+
+	/* FSYS */
+	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+	writel(CLK_SRC_ISP_VAL, &clk->src_isp);
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+	writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
+
+	writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
+
+	writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
+	writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
+	writel(CLK_DIV_G2D, &clk->div_g2d);
+
+	writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
+	writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+	writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
+}
+
+void system_clock_init(void)
+{
+	if (proid_is_exynos5420())
+		exynos5420_system_clock_init();
+	else
+		exynos5250_system_clock_init();
+}
+
 void clock_init_dp_clock(void)
 {
 	struct exynos5_clock *clk =

arch/arm/include/asm/arch-exynos/clk.h

@@ -14,6 +14,7 @@
 #define HPLL	3
 #define VPLL	4
 #define BPLL	5
+#define RPLL	6
 
 enum pll_src_bit {
 	EXYNOS_SRC_MPLL = 6,

arch/arm/include/asm/arch-exynos/clock.h

@@ -858,6 +858,500 @@ struct exynos5_clock {
 	unsigned char	res123[0xf5d8];
 };
 
+struct exynos5420_clock {
+	unsigned int	apll_lock;			/* 0x10010000 */
+	unsigned char	res1[0xfc];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res2[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res3[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res4[0xfc];
+	unsigned int	div_cpu0;		/* 0x10010500 */
+	unsigned int	div_cpu1;
+	unsigned char	res5[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res6[0xf8];
+	unsigned int	gate_bus_cpu;
+	unsigned char	res7[0xfc];
+	unsigned int	gate_sclk_cpu;
+	unsigned char	res8[0x1fc];
+	unsigned int	clkout_cmu_cpu;		/* 0x10010a00 */
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res9[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned char	res10[0x4];
+	unsigned int	arm_ema_ctrl;
+	unsigned int	arm_ema_status;
+	unsigned char	res11[0x10];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctrl2;
+	unsigned char	res12[0xd8];
+	unsigned int	apll_con0_l8;		/* 0x1001100 */
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res13[0xdc];
+	unsigned int	apll_con1_l8;		/* 0x10011200 */
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res14[0xe0];
+	unsigned int	clkdiv_iem_l8;
+	unsigned int	clkdiv_iem_l7;		/* 0x10011304 */
+	unsigned int	clkdiv_iem_l6;
+	unsigned int	clkdiv_iem_l5;
+	unsigned int	clkdiv_iem_l4;
+	unsigned int	clkdiv_iem_l3;
+	unsigned int	clkdiv_iem_l2;
+	unsigned int	clkdiv_iem_l1;
+	unsigned char	res15[0xe0];
+	unsigned int	l2_status;
+	unsigned char	res16[0x0c];
+	unsigned int	cpu_status;		/* 0x10011410 */
+	unsigned char	res17[0x0c];
+	unsigned int	ptm_status;
+	unsigned char	res18[0xbdc];
+	unsigned int	cmu_cpu_spare0;
+	unsigned int	cmu_cpu_spare1;
+	unsigned int	cmu_cpu_spare2;
+	unsigned int	cmu_cpu_spare3;
+	unsigned int	cmu_cpu_spare4;
+	unsigned char	res19[0x1fdc];
+	unsigned int	cmu_cpu_version;
+	unsigned char	res20[0x20c];
+	unsigned int	src_cperi0;		/* 0x10014200 */
+	unsigned int	src_cperi1;
+	unsigned char	res21[0xf8];
+	unsigned int	src_mask_cperi;
+	unsigned char	res22[0x100];
+	unsigned int	mux_stat_cperi1;
+	unsigned char	res23[0xfc];
+	unsigned int	div_cperi1;
+	unsigned char	res24[0xfc];
+	unsigned int	div_stat_cperi1;
+	unsigned char	res25[0xf8];
+	unsigned int	gate_bus_cperi0;	/* 0x10014700 */
+	unsigned int	gate_bus_cperi1;
+	unsigned char	res26[0xf8];
+	unsigned int	gate_sclk_cperi;
+	unsigned char	res27[0xfc];
+	unsigned int	gate_ip_cperi;
+	unsigned char	res28[0xfc];
+	unsigned int	clkout_cmu_cperi;
+	unsigned int	clkout_cmu_cperi_div_stat;
+	unsigned char	res29[0x5f8];
+	unsigned int	dcgidx_map0;		/* 0x10015000 */
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res30[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res31[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res32[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res33[0x18];
+	unsigned int	dvsemclk_en;		/* 0x10015080 */
+	unsigned int	maxperf;
+	unsigned char	res34[0x2e78];
+	unsigned int	cmu_cperi_spare0;
+	unsigned int	cmu_cperi_spare1;
+	unsigned int	cmu_cperi_spare2;
+	unsigned int	cmu_cperi_spare3;
+	unsigned int	cmu_cperi_spare4;
+	unsigned int	cmu_cperi_spare5;
+	unsigned int	cmu_cperi_spare6;
+	unsigned int	cmu_cperi_spare7;
+	unsigned int	cmu_cperi_spare8;
+	unsigned char	res35[0xcc];
+	unsigned int	cmu_cperi_version;		/* 0x10017ff0 */
+	unsigned char	res36[0x50c];
+	unsigned int	div_g2d;
+	unsigned char	res37[0xfc];
+	unsigned int	div_stat_g2d;
+	unsigned char	res38[0xfc];
+	unsigned int	gate_bus_g2d;
+	unsigned char	res39[0xfc];
+	unsigned int	gate_ip_g2d;
+	unsigned char	res40[0x1fc];
+	unsigned int	clkout_cmu_g2d;
+	unsigned int	clkout_cmu_g2d_div_stat;	/* 0x10018a04 */
+	unsigned char	res41[0xf8];
+	unsigned int	cmu_g2d_spare0;
+	unsigned int	cmu_g2d_spare1;
+	unsigned int	cmu_g2d_spare2;
+	unsigned int	cmu_g2d_spare3;
+	unsigned int	cmu_g2d_spare4;
+	unsigned char	res42[0x34dc];
+	unsigned int	cmu_g2d_version;
+	unsigned char	res43[0x30c];
+	unsigned int	div_cmu_isp0;
+	unsigned int	div_cmu_isp1;
+	unsigned int	div_isp2;		/* 0x1001c308 */
+	unsigned char	res44[0xf4];
+	unsigned int	div_stat_cmu_isp0;
+	unsigned int	div_stat_cmu_isp1;
+	unsigned int	div_stat_isp2;
+	unsigned char	res45[0x2f4];
+	unsigned int	gate_bus_isp0;
+	unsigned int	gate_bus_isp1;
+	unsigned int	gate_bus_isp2;
+	unsigned int	gate_bus_isp3;
+	unsigned char	res46[0xf0];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res47[0xf8];
+	unsigned int	gate_sclk_isp;
+	unsigned char	res48[0x0c];
+	unsigned int	mcuisp_pwr_ctrl;		/* 0x1001c910 */
+	unsigned char	res49[0x0ec];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_isp_div_stat;
+	unsigned char	res50[0xf8];
+	unsigned int	cmu_isp_spare0;
+	unsigned int	cmu_isp_spare1;
+	unsigned int	cmu_isp_spare2;
+	unsigned int	cmu_isp_spare3;
+	unsigned char	res51[0x34e0];
+	unsigned int	cmu_isp_version;
+	unsigned char	res52[0x2c];
+	unsigned int	cpll_lock;			/* 10020020 */
+	unsigned char	res53[0xc];
+	unsigned int	dpll_lock;
+	unsigned char	res54[0xc];
+	unsigned int	epll_lock;
+	unsigned char	res55[0xc];
+	unsigned int	rpll_lock;
+	unsigned char	res56[0xc];
+	unsigned int	ipll_lock;
+	unsigned char	res57[0xc];
+	unsigned int	spll_lock;
+	unsigned char	res58[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res59[0xc];
+	unsigned int	mpll_lock;
+	unsigned char	res60[0x8c];
+	unsigned int	cpll_con0;			/* 10020120 */
+	unsigned int	cpll_con1;
+	unsigned int	dpll_con0;
+	unsigned int	dpll_con1;
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res601[0x4];
+	unsigned int	rpll_con0;
+	unsigned int	rpll_con1;
+	unsigned int	rpll_con2;
+	unsigned char	res602[0x4];
+	unsigned int	ipll_con0;
+	unsigned int	ipll_con1;
+	unsigned char	res61[0x8];
+	unsigned int	spll_con0;
+	unsigned int	spll_con1;
+	unsigned char	res62[0x8];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned char	res63[0x8];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res64[0x78];
+	unsigned int	src_top0;		/* 0x10020200 */
+	unsigned int	src_top1;
+	unsigned int	src_top2;
+	unsigned int	src_top3;
+	unsigned int	src_top4;
+	unsigned int	src_top5;
+	unsigned int	src_top6;
+	unsigned int	src_top7;
+	unsigned char	res65[0xc];
+	unsigned int	src_disp10;		/* 0x1002022c */
+	unsigned char	res66[0x10];
+	unsigned int	src_mau;
+	unsigned int	src_fsys;
+	unsigned char	res67[0x8];
+	unsigned int	src_peric0;
+	unsigned int	src_peric1;
+	unsigned char	res68[0x18];
+	unsigned int	src_isp;
+	unsigned char	res69[0x0c];
+	unsigned int	src_top10;
+	unsigned int	src_top11;
+	unsigned int	src_top12;
+	unsigned char	res70[0x74];
+	unsigned int	src_mask_top0;
+	unsigned int	src_mask_top1;
+	unsigned int	src_mask_top2;
+	unsigned char	res71[0x10];
+	unsigned int	src_mask_top7;
+	unsigned char	res72[0xc];
+	unsigned int	src_mask_disp10;	/* 0x1002032c */
+	unsigned char	res73[0x4];
+	unsigned int	src_mask_mau;
+	unsigned char	res74[0x8];
+	unsigned int	src_mask_fsys;
+	unsigned char	res75[0xc];
+	unsigned int	src_mask_peric0;
+	unsigned int	src_mask_peric1;
+	unsigned char	res76[0x18];
+	unsigned int	src_mask_isp;
+	unsigned char	res77[0x8c];
+	unsigned int	mux_stat_top0;		/* 0x10020400 */
+	unsigned int	mux_stat_top1;
+	unsigned int	mux_stat_top2;
+	unsigned int	mux_stat_top3;
+	unsigned int	mux_stat_top4;
+	unsigned int	mux_stat_top5;
+	unsigned int	mux_stat_top6;
+	unsigned int	mux_stat_top7;
+	unsigned char	res78[0x60];
+	unsigned int	mux_stat_top10;
+	unsigned int	mux_stat_top11;
+	unsigned int	mux_stat_top12;
+	unsigned char	res79[0x74];
+	unsigned int	div_top0;		/* 0x10020500 */
+	unsigned int	div_top1;
+	unsigned int	div_top2;
+	unsigned char	res80[0x20];
+	unsigned int	div_disp10;
+	unsigned char	res81[0x14];
+	unsigned int	div_mau;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned char	res82[0x4];
+	unsigned int	div_peric0;
+	unsigned int	div_peric1;
+	unsigned int	div_peric2;
+	unsigned int	div_peric3;
+	unsigned int	div_peric4;		/* 0x10020568 */
+	unsigned char	res83[0x14];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned char	res84[0x8];
+	unsigned int	clkdiv2_ratio;
+	unsigned char	res850[0xc];
+	unsigned int	clkdiv4_ratio;
+	unsigned char	res85[0x5c];
+	unsigned int	div_stat_top0;
+	unsigned int	div_stat_top1;
+	unsigned int	div_stat_top2;
+	unsigned char	res86[0x20];
+	unsigned int	div_stat_disp10;
+	unsigned char	res87[0x14];
+	unsigned int	div_stat_mau;		/* 0x10020644 */
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned char	res88[0x4];
+	unsigned int	div_stat_peric0;
+	unsigned int	div_stat_peric1;
+	unsigned int	div_stat_peric2;
+	unsigned int	div_stat_peric3;
+	unsigned int	div_stat_peric4;
+	unsigned char	res89[0x14];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned char	res90[0x8];
+	unsigned int	clkdiv2_stat0;
+	unsigned char	res91[0xc];
+	unsigned int	clkdiv4_stat;
+	unsigned char	res92[0x5c];
+	unsigned int	gate_bus_top;		/* 0x10020700 */
+	unsigned char	res93[0xc];
+	unsigned int	gate_bus_gscl0;
+	unsigned char	res94[0xc];
+	unsigned int	gate_bus_gscl1;
+	unsigned char	res95[0x4];
+	unsigned int	gate_bus_disp1;
+	unsigned char	res96[0x4];
+	unsigned int	gate_bus_wcore;
+	unsigned int	gate_bus_mfc;
+	unsigned int	gate_bus_g3d;
+	unsigned int	gate_bus_gen;
+	unsigned int	gate_bus_fsys0;
+	unsigned int	gate_bus_fsys1;
+	unsigned int	gate_bus_fsys2;
+	unsigned int	gate_bus_mscl;
+	unsigned int	gate_bus_peric;
+	unsigned int	gate_bus_peric1;
+	unsigned char	res97[0x8];
+	unsigned int	gate_bus_peris0;
+	unsigned int	gate_bus_peris1;	/* 0x10020764 */
+	unsigned char	res98[0x8];
+	unsigned int	gate_bus_noc;
+	unsigned char	res99[0xac];
+	unsigned int	gate_top_sclk_gscl;
+	unsigned char	res1000[0x4];
+	unsigned int	gate_top_sclk_disp1;
+	unsigned char	res100[0x10];
+	unsigned int	gate_top_sclk_mau;
+	unsigned int	gate_top_sclk_fsys;
+	unsigned char	res101[0xc];
+	unsigned int	gate_top_sclk_peric;
+	unsigned char	res102[0xc];
+	unsigned int	gate_top_sclk_cperi;
+	unsigned char	res103[0xc];
+	unsigned int	gate_top_sclk_isp;
+	unsigned char	res104[0x9c];
+	unsigned int	gate_ip_gscl0;
+	unsigned char	res105[0xc];
+	unsigned int	gate_ip_gscl1;
+	unsigned char	res106[0x4];
+	unsigned int	gate_ip_disp1;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_gen;		/* 0x10020934 */
+	unsigned char	res107[0xc];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res108[0x8];
+	unsigned int	gate_ip_peric;
+	unsigned char	res109[0xc];
+	unsigned int	gate_ip_peris;
+	unsigned char	res110[0xc];
+	unsigned int	gate_ip_mscl;
+	unsigned char	res111[0xc];
+	unsigned int	gate_ip_block;
+	unsigned char	res112[0xc];
+	unsigned int	bypass;
+	unsigned char	res113[0x6c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res114[0xf8];
+	unsigned int	clkout_top_spare0;
+	unsigned int	clkout_top_spare1;
+	unsigned int	clkout_top_spare2;
+	unsigned int	clkout_top_spare3;
+	unsigned char	res115[0x34e0];
+	unsigned int	clkout_top_version;
+	unsigned char	res116[0xc01c];
+	unsigned int	bpll_lock;			/* 0x10030010 */
+	unsigned char	res117[0xfc];
+	unsigned int	bpll_con0;
+	unsigned int	bpll_con1;
+	unsigned char	res118[0xe8];
+	unsigned int	src_cdrex;
+	unsigned char	res119[0x1fc];
+	unsigned int	mux_stat_cdrex;
+	unsigned char	res120[0xfc];
+	unsigned int	div_cdrex0;
+	unsigned int	div_cdrex1;
+	unsigned char	res121[0xf8];
+	unsigned int	div_stat_cdrex;
+	unsigned char	res1211[0xfc];
+	unsigned int	gate_bus_cdrex;
+	unsigned int	gate_bus_cdrex1;
+	unsigned char	res122[0x1f8];
+	unsigned int	gate_ip_cdrex;
+	unsigned char	res123[0x10];
+	unsigned int	dmc_freq_ctrl;		/* 0x10030914 */
+	unsigned char	res124[0x4];
+	unsigned int	pause;
+	unsigned int	ddrphy_lock_ctrl;
+	unsigned char	res125[0xdc];
+	unsigned int	clkout_cmu_cdrex;
+	unsigned int	clkout_cmu_cdrex_div_stat;
+	unsigned char	res126[0x8];
+	unsigned int	lpddr3phy_ctrl;
+	unsigned int	lpddr3phy_con0;
+	unsigned int	lpddr3phy_con1;
+	unsigned int	lpddr3phy_con2;
+	unsigned int	lpddr3phy_con3;
+	unsigned int	lpddr3phy_con4;
+	unsigned int	lpddr3phy_con5;		/* 0x10030a28 */
+	unsigned int	pll_div2_sel;
+	unsigned char	res127[0xd0];
+	unsigned int	cmu_cdrex_spare0;
+	unsigned int	cmu_cdrex_spare1;
+	unsigned int	cmu_cdrex_spare2;
+	unsigned int	cmu_cdrex_spare3;
+	unsigned int	cmu_cdrex_spare4;
+	unsigned char	res128[0x34dc];
+	unsigned int	cmu_cdrex_version;		/* 0x10033ff0 */
+	unsigned char	res129[0x400c];
+	unsigned int	kpll_lock;
+	unsigned char	res130[0xfc];
+	unsigned int	kpll_con0;
+	unsigned int	kpll_con1;
+	unsigned char	res131[0xf8];
+	unsigned int	src_kfc;
+	unsigned char	res132[0x1fc];
+	unsigned int	mux_stat_kfc;		/* 0x10038400 */
+	unsigned char	res133[0xfc];
+	unsigned int	div_kfc0;
+	unsigned char	res134[0xfc];
+	unsigned int	div_stat_kfc0;
+	unsigned char	res135[0xfc];
+	unsigned int	gate_bus_cpu_kfc;
+	unsigned char	res136[0xfc];
+	unsigned int	gate_sclk_cpu_kfc;
+	unsigned char	res137[0x1fc];
+	unsigned int	clkout_cmu_kfc;
+	unsigned int	clkout_cmu_kfc_div_stat;	/* 0x10038a04 */
+	unsigned char	res138[0x5f8];
+	unsigned int	armclk_stopctrl_kfc;
+	unsigned char	res139[0x4];
+	unsigned int	armclk_ema_ctrl_kfc;
+	unsigned int	armclk_ema_status_kfc;
+	unsigned char	res140[0x10];
+	unsigned int	pwr_ctrl_kfc;
+	unsigned int	pwr_ctrl2_kfc;
+	unsigned char	res141[0xd8];
+	unsigned int	kpll_con0_l8;
+	unsigned int	kpll_con0_l7;
+	unsigned int	kpll_con0_l6;
+	unsigned int	kpll_con0_l5;
+	unsigned int	kpll_con0_l4;
+	unsigned int	kpll_con0_l3;
+	unsigned int	kpll_con0_l2;
+	unsigned int	kpll_con0_l1;
+	unsigned int	iem_control_kfc;		/* 0x10039120 */
+	unsigned char	res142[0xdc];
+	unsigned int	kpll_con1_l8;
+	unsigned int	kpll_con1_l7;
+	unsigned int	kpll_con1_l6;
+	unsigned int	kpll_con1_l5;
+	unsigned int	kpll_con1_l4;
+	unsigned int	kpll_con1_l3;
+	unsigned int	kpll_con1_l2;
+	unsigned int	kpll_con1_l1;
+	unsigned char	res143[0xe0];
+	unsigned int	clkdiv_iem_l8_kfc;		/* 0x10039300 */
+	unsigned int	clkdiv_iem_l7_kfc;
+	unsigned int	clkdiv_iem_l6_kfc;
+	unsigned int	clkdiv_iem_l5_kfc;
+	unsigned int	clkdiv_iem_l4_kfc;
+	unsigned int	clkdiv_iem_l3_kfc;
+	unsigned int	clkdiv_iem_l2_kfc;
+	unsigned int	clkdiv_iem_l1_kfc;
+	unsigned char	res144[0xe0];
+	unsigned int	l2_status_kfc;
+	unsigned char	res145[0xc];
+	unsigned int	cpu_status_kfc;		/* 0x10039410 */
+	unsigned char	res146[0xc];
+	unsigned int	ptm_status_kfc;
+	unsigned char	res147[0xbdc];
+	unsigned int	cmu_kfc_spare0;
+	unsigned int	cmu_kfc_spare1;
+	unsigned int	cmu_kfc_spare2;
+	unsigned int	cmu_kfc_spare3;
+	unsigned int	cmu_kfc_spare4;
+	unsigned char	res148[0x1fdc];
+	unsigned int	cmu_kfc_version;		/* 0x1003bff0 */
+};
+
 /* structure for epll configuration used in audio clock configuration */
 struct set_epll_con_val {
 	unsigned int freq_out;		/* frequency out */