SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
enums yield no user and therefore support seems to be incomplete. Remove
these configs so as to avoid confusion.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

SPL only needs to be able to read from SPI Flash to load next stage and
does not really need write/erase etc. Therefore in order to reduce SPI
Flash code size in SPL, enable SPI_FLASH_TINY, that only supports
reading from SPI flash, as default.

Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR,
SPI_FLASH_TINY is not enabled for boards with SPI controllers that
cannot support 4 byte addressing.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.

Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible
SPI Flash device nodes. Therefore make U-Boot also to look for the same
compatible string so that we can use Linux DTS files as is.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Add hweight*() macros required for moving to new SF layer
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Tested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NStefan Roese <sr@denx.de>
Tested-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

In arch/sandbox/include/asm/types.h we have
Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as
CONFIG_PHYS64 is not set

This messes up the current logic of GENMASK macro due to mismatch b/w
size of unsigned long (64 bit) and that of BITS_PER_LONG.
Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32
based on the host machine on which its being compiled.

Without this patch:
GENMASK(14,0) => 0x7fffffffffff
After this patch:
GENMASK(14,0) => 0x7fff
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Completely move CONFIG_SPI_FLASH from remaining board header files to
defconfigs
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs

- MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
- MIPS: mt76xx: fix timer frequency

- Various TI platforms have been updated and DTS files re-synced and
  options disabled if not used or migrated to the DM versions
- Improvements to the dumpimage tool
- Rename SPL FAT/EXT filesystem support symbols for consistency and then
  allow them to be used to save more space in SPL.
- More lmb fixes
- Partial migration of CONFIG_BUILD_TARGET

Now that BUILD_TARGET is in Kconfig we can define a default for boards
using the Kirkwood SoC.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>

Migrate CONFIG_BUILD_TARGET into Kconfig.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

This adds one test case that checks that allocation with multiple
DRAM banks works correctly.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This fixes the automatic lmb initialization and reservation for boards
with more than one DRAM bank.

This fixes the CVE-2018-18439 and -18440 fixes that only allowed to load
files into the firs DRAM bank from fs and via tftp.
Found-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Help message isn't clear over the use of the "-T" option (it's to declare
the type of image that the tool is operating on), which also is optional
as it defaults to the default image type. It's also missing a description
of the "-o" option, so add it.
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>

The utility dumpimage has error paths that display the usage and others
that exit without displaying usage. Add an explicit help option to
dumpimage to display the usage and remove it's use in error paths to make
the error messages more obvious and errors paths more consistent.
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>

There are 3 supported modes of operation:

1) Show version
2) List image contents
3) Extract image component

Option (1) terminates early, so only options (2) and (3) remain. Remove
redundant check for these modes.
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>

The dump image utility has very confusing syntax. If called to list image
contents ("-l") it takes the image name as a positional argument. If the
utility is called to extract something from the image, the image must be
provided via the optional argument "-i" as well as the positional argument
but the value passed in the positional argument will be completely
ignored.

Simplify dumpimage by always providing the image as the first positional
argument. Assume we want to dump something from the image if we do not
provide the "-l" option for now.
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>

The dumpimage utility errors out in a number of places without providing
sufficient feedback to allow the user to easily determine what they have
done wrong. Add addtional error messages to make the cause of the failure
more obvious.
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>

The OMAP36 and DM37 TRM state to disable extneded drain IO before
changing the PBIAS.  This patch does this before pmic writes if
the CONFIG_MMC_OMAP36XX_PINS flag is set and the cpu family is
omap36xx
Signed-off-by: NAdam Ford <aford173@gmail.com>

With the latest changes to add support for the Chromebook Bob,
initialisation through debug_uart_init() did no longer get called for
other targets.

Fix this, by moving debug_uart_init() out of the Bob-specific
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

As we're working on the next update of our ATF (and U-Boot and the ATF
are out-of-sync), let's temporarily enable SPL_ATF_NO_PLATFORM_PARAM to
reduce compatibility issues.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing.  Add it here, so we can select the
pinctrl-driver for SPL.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

This adds a MAINTAINER entry for chromebook_speedy.

Without this, we get the following warnings from the maintainers
check:
    WARNING: no status info for 'chromebook_minnie'
    WARNING: no maintainers for 'chromebook_minnie'
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Add some U-Boot-specific settings. These should really go in the
*u-boot.dtsi file, but it seems that rk3399 does not use that yet.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

At present this enum is only available to rk3288. Move it so that other
rockchip SoCs can access it. It is needed for the SPL GPIO driver for
rk3999 in a later patch.

Also adjust the enum name to lower case.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>