Skip to content

U
U-Boot.Mirror

OS / U-Boot.Mirror

通知 1
Star 0
Fork 0
U
U-Boot.Mirror

体验新版 GitCode，发现更多精彩内容 >>

提交 e5fd39c8 编写于 作者: T Tom Rini
浏览文件
操作

Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip 

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs
上级 544d5e98 73ced87e
展开全部 隐藏空白更改
内联 并排
Showing with 7516 addition and 6775 deletion
arch/arm/dts/Makefile
浏览文件 @ e5fd39c8
......@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3399-ficus.dtb \
......
arch/arm/dts/rk322x.dtsi
浏览文件 @ e5fd39c8
......@@ -206,7 +206,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
pinctrl-0 = <&uart21_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
......@@ -748,7 +748,7 @@
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
};
......@@ -760,6 +760,13 @@
rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2-1 {
uart21_xfer: uart21-xfer {
rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
<1 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
};
dmc: dmc@11200000 {
......
arch/arm/dts/rk3288-veyron-jerry.dts
浏览文件 @ e5fd39c8
......@@ -52,6 +52,18 @@
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
sound {
compatible = "rockchip,audio-max98090-jerry";
cpu {
sound-dai = <&i2s 0>;
};
codec {
sound-dai = <&max98090 0>;
};
};
};
&dmc {
......
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2015 Google, Inc
*/
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x1>;
rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
arch/arm/dts/rk3288-veyron-speedy.dts 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Speedy Rev 1+ board device tree source
*
* Copyright 2015 Google, Inc
*/
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
#include "cros-ec-sbs.dtsi"
#include "rk3288-veyron-speedy-u-boot.dtsi"
/ {
model = "Google Speedy";
compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&avdd_1v8_disp_en>;
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwr_en>;
regulator-name = "backlight_regulator";
vin-supply = <&vcc33_sys>;
startup-delay-us = <15000>;
};
};
&backlight {
power-supply = <&backlight_regulator>;
};
&cpu_alert0 {
temperature = <65000>;
};
&cpu_alert1 {
temperature = <70000>;
};
&edp {
/delete-property/pinctrl-names;
/delete-property/pinctrl-0;
force-hpd;
};
&panel {
power-supply = <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
};
&sdmmc {
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
&sdmmc_bus4>;
};
&vcc_5v {
enable-active-high;
gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&drv_5v>;
};
&vcc50_hdmi {
enable-active-high;
gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc50_hdmi_en>;
};
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_enable_h: lcd-en {
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
};
avdd_1v8_disp_en: avdd-1v8-disp-en {
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dvs_1: dvs-1 {
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
arch/arm/dts/rk3288-veyron.dtsi
浏览文件 @ e5fd39c8
......@@ -484,6 +484,7 @@
max98090: max98090@10 {
compatible = "maxim,max98090";
reg = <0x10>;
#sound-dai-cells = <0>;
interrupt-parent = <&gpio6>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
......
arch/arm/dts/rk3288.dtsi
浏览文件 @ e5fd39c8
......@@ -649,6 +649,7 @@
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
......
arch/arm/dts/rk3399-firefly.dts
浏览文件 @ e5fd39c8
......@@ -15,7 +15,7 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &sdhci, &sdmmc;
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
backlight: backlight {
......
arch/arm/dts/rk3399-gru-bob.dts 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Gru-Bob Rev 4+ board device tree source
*
* Copyright 2018 Google, Inc
*/
/dts-v1/;
#include "rk3399-gru-chromebook.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
/ {
model = "Google Bob";
compatible = "google,bob-rev13", "google,bob-rev12",
"google,bob-rev11", "google,bob-rev10",
"google,bob-rev9", "google,bob-rev8",
"google,bob-rev7", "google,bob-rev6",
"google,bob-rev5", "google,bob-rev4",
"google,bob", "google,gru", "rockchip,rk3399";
edp_panel: edp-panel {
compatible = "boe,nv101wxmn51", "simple-panel";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
ports {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
&ap_i2c_ts {
touchscreen: touchscreen@10 {
compatible = "elan,ekth3500";
reg = <0x10>;
interrupt-parent = <&gpio3>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int_l &touch_reset_l>;
reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
};
&ap_i2c_tp {
trackpad: trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_int_l>;
wakeup-source;
};
};
&backlight {
pwms = <&cros_ec_pwm 0>;
};
&cpu_alert0 {
temperature = <65000>;
};
&cpu_alert1 {
temperature = <70000>;
};
&spi0 {
status = "okay";
};
&pinctrl {
tpm {
h1_int_od_l: h1-int-od-l {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
arch/arm/dts/rk3399-gru-chromebook.dtsi 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Gru-Chromebook shared properties
*
* Copyright 2018 Google, Inc
*/
#include "rk3399-gru.dtsi"
/ {
pp900_ap: pp900-ap {
compatible = "regulator-fixed";
regulator-name = "pp900_ap";
/* EC turns on w/ pp900_ap_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&ppvar_sys>;
};
/* EC turns on w/ pp900_usb_en */
pp900_usb: pp900-ap {
};
/* EC turns on w/ pp900_pcie_en */
pp900_pcie: pp900-ap {
};
pp3000: pp3000 {
compatible = "regulator-fixed";
regulator-name = "pp3000";
pinctrl-names = "default";
pinctrl-0 = <&pp3000_en>;
enable-active-high;
gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
vin-supply = <&ppvar_sys>;
};
ppvar_centerlogic_pwm: ppvar-centerlogic-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_centerlogic_pwm";
pwms = <&pwm3 0 3337 0>;
pwm-supply = <&ppvar_sys>;
pwm-dutycycle-range = <100 0>;
pwm-dutycycle-unit = <100>;
/* EC turns on w/ ppvar_centerlogic_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <799434>;
regulator-max-microvolt = <1049925>;
};
ppvar_centerlogic: ppvar-centerlogic {
compatible = "vctrl-regulator";
regulator-name = "ppvar_centerlogic";
regulator-min-microvolt = <799434>;
regulator-max-microvolt = <1049925>;
ctrl-supply = <&ppvar_centerlogic_pwm>;
ctrl-voltage-range = <799434 1049925>;
regulator-settling-time-up-us = <378>;
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
/* Schematics call this PPVAR even though it's fixed */
ppvar_logic: ppvar-logic {
compatible = "regulator-fixed";
regulator-name = "ppvar_logic";
/* EC turns on w/ ppvar_logic_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&ppvar_sys>;
};
pp1800_audio: pp1800-audio {
compatible = "regulator-fixed";
regulator-name = "pp1800_audio";
pinctrl-names = "default";
pinctrl-0 = <&pp1800_audio_en>;
enable-active-high;
gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&pp1800>;
};
/* gpio is shared with pp3300_wifi_bt */
pp1800_pcie: pp1800-pcie {
compatible = "regulator-fixed";
regulator-name = "pp1800_pcie";
pinctrl-names = "default";
pinctrl-0 = <&wlan_module_pd_l>;
enable-active-high;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
/*
* Need to wait 1ms + ramp-up time before we can power on WiFi.
* This has been approximated as 8ms total.
*/
regulator-enable-ramp-delay = <8000>;
vin-supply = <&pp1800>;
};
/* Always on; plain and simple */
pp3000_ap: pp3000_emmc: pp3000 {
};
pp1500_ap_io: pp1500-ap-io {
compatible = "regulator-fixed";
regulator-name = "pp1500_ap_io";
pinctrl-names = "default";
pinctrl-0 = <&pp1500_en>;
enable-active-high;
gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vin-supply = <&pp1800>;
};
pp3300_disp: pp3300-disp {
compatible = "regulator-fixed";
regulator-name = "pp3300_disp";
pinctrl-names = "default";
pinctrl-0 = <&pp3300_disp_en>;
enable-active-high;
gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
vin-supply = <&pp3300>;
};
/* EC turns on w/ pp3300_usb_en_l */
pp3300_usb: pp3300 {
};
/* gpio is shared with pp1800_pcie and pinctrl is set there */
pp3300_wifi_bt: pp3300-wifi-bt {
compatible = "regulator-fixed";
regulator-name = "pp3300_wifi_bt";
enable-active-high;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300>;
};
/*
* This is a bit of a hack. The WiFi module should be reset at least
* 1ms after its regulators have ramped up (max rampup time is ~7ms).
* With some stretching of the imagination, we can call the 1.8V
* regulator a supply.
*/
wlan_pd_n: wlan-pd-n {
compatible = "regulator-fixed";
regulator-name = "wlan_pd_n";
pinctrl-names = "default";
pinctrl-0 = <&wlan_module_reset_l>;
enable-active-high;
gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp1800_pcie>;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58
59 60 61 62 63 64 65 66 67 68 69 70 71 72
73 74 75 76 77 78 79 80 81 82 83 84 85 86
87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
default-brightness-level = <51>;
enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
power-supply = <&pp3300_disp>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwm-delay-us = <10000>;
};
};
&ppvar_bigcpu {
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
&ppvar_litcpu {
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
&ppvar_gpu {
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
&cdn_dp {
extcon = <&usbc_extcon0>, <&usbc_extcon1>;
};
&edp {
status = "okay";
rockchip,panel = <&edp_panel>;
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
ap_i2c_mic: &i2c1 {
status = "okay";
clock-frequency = <400000>;
/* These are relatively safe rise/fall times */
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
headsetcodec: rt5514@57 {
compatible = "realtek,rt5514";
reg = <0x57>;
realtek,dmic-init-delay-ms = <20>;
};
};
ap_i2c_tp: &i2c5 {
status = "okay";
clock-frequency = <400000>;
/* These are relatively safe rise/fall times */
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
/*
* Note strange pullup enable. Apparently this avoids leakage but
* still allows us to get nice 4.7K pullups for high speed i2c
* transfers. Basically we want the pullup on whenever the ap is
* alive, so the "en" pin just gets set to output high.
*/
pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>;
};
&cros_ec {
cros_ec_pwm: ec-pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};
usbc_extcon1: extcon@1 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <1>;
#extcon-cells = <0>;
};
};
&sound {
rockchip,codec = <&max98357a &headsetcodec
&codec &wacky_spi_audio &cdn_dp>;
};
&spi2 {
wacky_spi_audio: spi2@0 {
compatible = "realtek,rt5514";
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mic_int>;
/* May run faster once verified. */
spi-max-frequency = <10000000>;
wakeup-source;
};
};
&pci_rootport {
mvl_wifi: wifi@0,0 {
compatible = "pci1b4b,2b42";
reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
0x83010000 0x0 0x00100000 0x0 0x00100000>;
interrupt-parent = <&gpio0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&wlan_host_wake_l>;
wakeup-source;
};
};
&tcphy1 {
status = "okay";
extcon = <&usbc_extcon1>;
};
&u2phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_1 {
status = "okay";
extcon = <&usbc_extcon1>;
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&pinctrl {
discrete-regulators {
pp1500_en: pp1500-en {
rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp1800_audio_en: pp1800-audio-en {
rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO
&pcfg_pull_down>;
};
pp3000_en: pp3000-en {
rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp3300_disp_en: pp3300-disp-en {
rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO
&pcfg_pull_none>;
};
wlan_module_pd_l: wlan-module-pd-l {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO
&pcfg_pull_down>;
};
};
};
&wifi {
wifi_perst_l: wifi-perst-l {
rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_host_wake_l: wlan-host-wake-l {
rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
arch/arm/dts/rk3399-gru-kevin.dts 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Gru-Kevin Rev 6+ board device tree source
*
* Copyright 2016-2017 Google, Inc
*/
/dts-v1/;
#include "rk3399-gru-chromebook.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
/*
* Kevin-specific things
*
* Things in this section should use names from Kevin schematic since no
* equivalent exists in Gru schematic. If referring to signals that exist
* in Gru we use the Gru names, though. Confusing enough for you?
*/
/ {
model = "Google Kevin";
compatible = "google,kevin-rev15", "google,kevin-rev14",
"google,kevin-rev13", "google,kevin-rev12",
"google,kevin-rev11", "google,kevin-rev10",
"google,kevin-rev9", "google,kevin-rev8",
"google,kevin-rev7", "google,kevin-rev6",
"google,kevin", "google,gru", "rockchip,rk3399";
/* Power tree */
p3_3v_dig: p3-3v-dig {
compatible = "regulator-fixed";
regulator-name = "p3.3v_dig";
pinctrl-names = "default";
pinctrl-0 = <&cpu3_pen_pwr_en>;
enable-active-high;
gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300>;
};
edp_panel: edp-panel {
compatible = "sharp,lq123p1jx31", "simple-panel";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
ports {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu {
compatible = "murata,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <25500>;
pulldown-ohm = <0>;
io-channels = <&saradc 2>;
#thermal-sensor-cells = <0>;
};
thermistor_ppvar_litcpu: thermistor-ppvar-litcpu {
compatible = "murata,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <25500>;
pulldown-ohm = <0>;
io-channels = <&saradc 3>;
#thermal-sensor-cells = <0>;
};
};
&backlight {
pwms = <&cros_ec_pwm 1>;
};
&gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
pen-insert {
label = "Pen Insert";
/* Insert = low, eject = high */
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
linux,code = <SW_PEN_INSERTED>;
linux,input-type = <EV_SW>;
wakeup-source;
};
};
&thermal_zones {
bigcpu_reg_thermal: bigcpu-reg-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&thermistor_ppvar_bigcpu 0>;
sustainable-power = <4000>;
ppvar_bigcpu_trips: trips {
ppvar_bigcpu_on: ppvar-bigcpu-on {
temperature = <40000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
ppvar_bigcpu_alert: ppvar-bigcpu-alert {
temperature = <50000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
ppvar_bigcpu_crit: ppvar-bigcpu-crit {
temperature = <90000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
map1 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
litcpu_reg_thermal: litcpu-reg-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&thermistor_ppvar_litcpu 0>;
sustainable-power = <4000>;
ppvar_litcpu_trips: trips {
ppvar_litcpu_on: ppvar-litcpu-on {
temperature = <40000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
ppvar_litcpu_alert: ppvar-litcpu-alert {
temperature = <50000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
ppvar_litcpu_crit: ppvar-litcpu-crit {
temperature = <90000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
};
};
ap_i2c_tpm: &i2c0 {
status = "okay";
clock-frequency = <400000>;
/* These are relatively safe rise/fall times. */
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
tpm: tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
powered-while-suspended;
};
};
ap_i2c_dig: &i2c2 {
status = "okay";
clock-frequency = <400000>;
/* These are relatively safe rise/fall times. */
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
digitizer: digitizer@9 {
/* wacom,w9013 */
compatible = "hid-over-i2c";
reg = <0x9>;
pinctrl-names = "default";
pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>;
vdd-supply = <&p3_3v_dig>;
post-power-on-delay-ms = <100>;
interrupt-parent = <&gpio2>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
hid-descr-addr = <0x1>;
};
};
/* Adjustments to things in the gru baseboard */
&ap_i2c_tp {
trackpad@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_int_l>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
linux,gpio-keymap = <KEY_RESERVED
KEY_RESERVED
KEY_RESERVED
BTN_LEFT>;
wakeup-source;
};
};
&ap_i2c_ts {
touchscreen@4b {
compatible = "atmel,maxtouch";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int_l>;
interrupt-parent = <&gpio3>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
};
};
&ppvar_bigcpu_pwm {
regulator-min-microvolt = <798674>;
regulator-max-microvolt = <1302172>;
};
&ppvar_bigcpu {
regulator-min-microvolt = <798674>;
regulator-max-microvolt = <1302172>;
ctrl-voltage-range = <798674 1302172>;
};
&ppvar_litcpu_pwm {
regulator-min-microvolt = <799065>;
regulator-max-microvolt = <1303738>;
};
&ppvar_litcpu {
regulator-min-microvolt = <799065>;
regulator-max-microvolt = <1303738>;
ctrl-voltage-range = <799065 1303738>;
};
&ppvar_gpu_pwm {
regulator-min-microvolt = <785782>;
regulator-max-microvolt = <1217729>;
};
&ppvar_gpu {
regulator-min-microvolt = <785782>;
regulator-max-microvolt = <1217729>;
ctrl-voltage-range = <785782 1217729>;
};
&ppvar_centerlogic_pwm {
regulator-min-microvolt = <800069>;
regulator-max-microvolt = <1049692>;
};
&ppvar_centerlogic {
regulator-min-microvolt = <800069>;
regulator-max-microvolt = <1049692>;
ctrl-voltage-range = <800069 1049692>;
};
&saradc {
status = "okay";
vref-supply = <&pp1800_ap_io>;
};
&mvl_wifi {
marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */
};
&pinctrl {
digitizer {
/* Has external pullup */
cpu1_dig_irq_l: cpu1-dig-irq-l {
rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* Has external pullup */
cpu1_dig_pdct_l: cpu1-dig-pdct-l {
rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
discrete-regulators {
cpu3_pen_pwr_en: cpu3-pen-pwr-en {
rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pen {
cpu1_pen_eject: cpu1-pen-eject {
rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
arch/arm/dts/rk3399-gru.dtsi 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Gru (and derivatives) board device tree source
*
* Copyright 2016-2017 Google, Inc
*/
#include <dt-bindings/input/input.h>
#include "rk3399.dtsi"
#include "rk3399-op1-opp.dtsi"
/ {
chosen {
u-boot,dm-pre-reloc;
stdout-path = "serial2:115200n8";
u-boot,spl-boot-order = &spi_flash;
};
config {
u-boot,spl-payload-offset = <0x40000>;
};
/*
* Power Tree
*
* In general an attempt is made to include all rails called out by
* the schematic as long as those rails interact in some way with
* the AP. AKA:
* - Rails that only connect to the EC (or devices that the EC talks to)
* are not included.
* - Rails _are_ included if the rails go to the AP even if the AP
* doesn't currently care about them / they are always on. The idea
* here is that it makes it easier to map to the schematic or extend
* later.
*
* If two rails are substantially the same from the AP's point of
* view, though, we won't create a full fixed regulator. We'll just
* put the child rail as an alias of the parent rail. Sometimes rails
* look the same to the AP because one of these is true:
* - The EC controls the enable and the EC always enables a rail as
* long as the AP is running.
* - The rails are actually connected to each other by a jumper and
* the distinction is just there to add clarity/flexibility to the
* schematic.
*/
ppvar_sys: ppvar-sys {
compatible = "regulator-fixed";
regulator-name = "ppvar_sys";
regulator-always-on;
regulator-boot-on;
};
pp1200_lpddr: pp1200-lpddr {
compatible = "regulator-fixed";
regulator-name = "pp1200_lpddr";
/* EC turns on w/ lpddr_pwr_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&ppvar_sys>;
};
pp1800: pp1800 {
compatible = "regulator-fixed";
regulator-name = "pp1800";
/* Always on when ppvar_sys shows power good */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&ppvar_sys>;
};
pp3300: pp3300 {
compatible = "regulator-fixed";
regulator-name = "pp3300";
/* Always on; plain and simple */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&ppvar_sys>;
};
pp5000: pp5000 {
compatible = "regulator-fixed";
regulator-name = "pp5000";
/* EC turns on w/ pp5000_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&ppvar_sys>;
};
ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_bigcpu_pwm";
pwms = <&pwm1 0 3337 0>;
pwm-supply = <&ppvar_sys>;
pwm-dutycycle-range = <100 0>;
pwm-dutycycle-unit = <100>;
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800107>;
regulator-max-microvolt = <1302232>;
};
ppvar_bigcpu: ppvar-bigcpu {
compatible = "vctrl-regulator";
regulator-name = "ppvar_bigcpu";
regulator-min-microvolt = <800107>;
regulator-max-microvolt = <1302232>;
ctrl-supply = <&ppvar_bigcpu_pwm>;
ctrl-voltage-range = <800107 1302232>;
regulator-settling-time-up-us = <322>;
};
ppvar_litcpu_pwm: ppvar-litcpu-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_litcpu_pwm";
pwms = <&pwm2 0 3337 0>;
pwm-supply = <&ppvar_sys>;
pwm-dutycycle-range = <100 0>;
pwm-dutycycle-unit = <100>;
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <797743>;
regulator-max-microvolt = <1307837>;
};
ppvar_litcpu: ppvar-litcpu {
compatible = "vctrl-regulator";
regulator-name = "ppvar_litcpu";
regulator-min-microvolt = <797743>;
regulator-max-microvolt = <1307837>;
ctrl-supply = <&ppvar_litcpu_pwm>;
ctrl-voltage-range = <797743 1307837>;
regulator-settling-time-up-us = <384>;
};
ppvar_gpu_pwm: ppvar-gpu-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_gpu_pwm";
pwms = <&pwm0 0 3337 0>;
pwm-supply = <&ppvar_sys>;
pwm-dutycycle-range = <100 0>;
pwm-dutycycle-unit = <100>;
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <786384>;
regulator-max-microvolt = <1217747>;
};
ppvar_gpu: ppvar-gpu {
compatible = "vctrl-regulator";
regulator-name = "ppvar_gpu";
regulator-min-microvolt = <786384>;
regulator-max-microvolt = <1217747>;
ctrl-supply = <&ppvar_gpu_pwm>;
ctrl-voltage-range = <786384 1217747>;
regulator-settling-time-up-us = <390>;
};
/* EC turns on w/ pp900_ddrpll_en */
pp900_ddrpll: pp900-ap {
};
/* EC turns on w/ pp900_pll_en */
pp900_pll: pp900-ap {
};
/* EC turns on w/ pp900_pmu_en */
pp900_pmu: pp900-ap {
};
/* EC turns on w/ pp1800_s0_en_l */
pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
};
/* EC turns on w/ pp1800_avdd_en_l */
pp1800_avdd: pp1800 {
};
/* EC turns on w/ pp1800_lid_en_l */
pp1800_lid: pp1800_mic: pp1800 {
};
/* EC turns on w/ lpddr_pwr_en */
pp1800_lpddr: pp1800 {
};
/* EC turns on w/ pp1800_pmu_en_l */
pp1800_pmu: pp1800 {
};
/* EC turns on w/ pp1800_usb_en_l */
pp1800_usb: pp1800 {
};
pp3000_sd_slot: pp3000-sd-slot {
compatible = "regulator-fixed";
regulator-name = "pp3000_sd_slot";
pinctrl-names = "default";
pinctrl-0 = <&sd_slot_pwr_en>;
enable-active-high;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3000>;
};
/*
* Technically, this is a small abuse of 'regulator-gpio'; this
* regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
* always on though, so it is sufficient to simply control the mux
* here.
*/
ppvar_sd_card_io: ppvar-sd-card-io {
compatible = "regulator-gpio";
regulator-name = "ppvar_sd_card_io";
pinctrl-names = "default";
pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
enable-active-high;
enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3000000 0x0>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
/* EC turns on w/ pp3300_trackpad_en_l */
pp3300_trackpad: pp3300-trackpad {
};
/* EC turns on w/ usb_a_en */
pp5000_usb_a_vbus: pp5000 {
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
wake_on_bt: wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
max98357a: max98357a {
compatible = "maxim,max98357a";
pinctrl-names = "default";
pinctrl-0 = <&sdmode_en>;
sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
sdmode-delay = <2>;
#sound-dai-cells = <0>;
status = "okay";
};
sound: sound {
compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <&i2s0 &i2s2>;
};
};
&cdn_dp {
status = "okay";
};
/*
* Set some suspend operating points to avoid OVP in suspend
*
* When we go into S3 ARM Trusted Firmware will transition our PWM regulators
* from wherever they're at back to the "default" operating point (whatever
* voltage we get when we set the PWM pins to "input").
*
* This quick transition under light load has the possibility to trigger the
* regulator "over voltage protection" (OVP).
*
* To make extra certain that we don't hit this OVP at suspend time, we'll
* transition to a voltage that's much closer to the default (~1.0 V) so that
* there will not be a big jump. Technically we only need to get within 200 mV
* of the default voltage, but the speed here should be fast enough and we need
* suspend/resume to be rock solid.
*/
&cluster0_opp {
opp05 {
opp-suspend;
};
};
&cluster1_opp {
opp06 {
opp-suspend;
};
};
&cpu_l0 {
cpu-supply = <&ppvar_litcpu>;
};
&cpu_l1 {
cpu-supply = <&ppvar_litcpu>;
};
&cpu_l2 {
cpu-supply = <&ppvar_litcpu>;
};
&cpu_l3 {
cpu-supply = <&ppvar_litcpu>;
};
&cpu_b0 {
cpu-supply = <&ppvar_bigcpu>;
};
&cpu_b1 {
cpu-supply = <&ppvar_bigcpu>;
};
&cru {
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>, <800000000>,
<100000000>, <50000000>,
<400000000>, <400000000>,
<200000000>,
<200000000>;
};
&emmc_phy {
status = "okay";
};
&gpu {
mali-supply = <&ppvar_gpu>;
status = "okay";
};
ap_i2c_ts: &i2c3 {
status = "okay";
clock-frequency = <400000>;
/* These are relatively safe rise/fall times */
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
};
ap_i2c_audio: &i2c8 {
status = "okay";
clock-frequency = <400000>;
/* These are relatively safe rise/fall times */
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
codec: da7219@1a {
compatible = "dlg,da7219";
reg = <0x1a>;
interrupt-parent = <&gpio1>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
dlg,micbias-lvl = <2600>;
dlg,mic-amp-in-sel = "diff";
pinctrl-names = "default";
pinctrl-0 = <&headset_int_l>;
VDD-supply = <&pp1800>;
VDDMIC-supply = <&pp3300>;
VDDIO-supply = <&pp1800>;
da7219_aad {
dlg,adc-1bit-rpt = <1>;
dlg,btn-avg = <4>;
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
dlg,jack-det-rate = "32ms_64ms";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;
dlg,d-b-btn-thr = <0x16>;
dlg,b-c-btn-thr = <0x21>;
dlg,c-mic-btn-thr = <0x3E>;
};
};
};
&i2s0 {
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
status = "okay";
audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
};
&pcie0 {
status = "okay";
ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
vpcie3v3-supply = <&pp3300_wifi_bt>;
vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
vpcie0v9-supply = <&pp900_pcie>;
pci_rootport: pcie@0,0 {
reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&pcie_phy {
status = "okay";
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&sdhci {
/*
* Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
* same (or nearly the same) performance for all eMMC that are intended
* to be used.
*/
assigned-clock-rates = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdmmc {
status = "okay";
/*
* Note: configure "sdmmc_cd" as card detect even though it's actually
* hooked to ground. Because we specified "cd-gpios" below dw_mmc
* should be ignoring card detect anyway. Specifying the pin as
* sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
* turned on that the system will still make sure the port is
* configured as SDMMC and not JTAG.
*/
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
&sdmmc_bus4>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&pp3000_sd_slot>;
vqmmc-supply = <&ppvar_sd_card_io>;
};
&spi1 {
status = "okay";
u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
spi_flash: spiflash@0 {
u-boot,dm-pre-reloc;
compatible = "jedec,spi-nor", "spi-flash";
reg = <0>;
/* May run faster once verified. */
spi-max-frequency = <10000000>;
};
};
&spi2 {
status = "okay";
};
&spi5 {
status = "okay";
spi-activate-delay = <100>;
spi-max-frequency = <3000000>;
spi-deactivate-delay = <200>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
i2c_tunnel: i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
google,remote-bus = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
usbc_extcon0: extcon@0 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
#extcon-cells = <0>;
};
};
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
&tcphy0 {
status = "okay";
extcon = <&usbc_extcon0>;
};
&u2phy0 {
status = "okay";
};
&u2phy0_host {
status = "okay";
};
&u2phy1_host {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&uart2 {
status = "okay";
u-boot,dm-pre-reloc;
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
extcon = <&usbc_extcon0>;
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
#include <cros-ec-keyboard.dtsi>
#include <cros-ec-sbs.dtsi>
&pinctrl {
/*
* pinctrl settings for pins that have no real owners.
*
* At the moment settings are identical for S0 and S3, but if we later
* need to configure things differently for S3 we'll adjust here.
*/
pinctrl-names = "default";
pinctrl-0 = <
&ap_pwroff /* AP will auto-assert this when in S3 */
&clk_32k /* This pin is always 32k on gru boards */
>;
pcfg_output_low: pcfg-output-low {
output-low;
};
pcfg_output_high: pcfg-output-high {
output-high;
};
pcfg_pull_none_8ma: pcfg-pull-none-8ma {
bias-disable;
drive-strength = <8>;
};
backlight-enable {
bl_en: bl-en {
rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cros-ec {
ec_ap_int_l: ec-ap-int-l {
rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
discrete-regulators {
sd_io_pwr_en: sd-io-pwr-en {
rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_pwr_1800_sel: sd-pwr-1800-sel {
rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_slot_pwr_en: sd-slot-pwr-en {
rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
&pcfg_pull_none>;
};
};
codec {
/* Has external pullup */
headset_int_l: headset-int-l {
rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
};
mic_int: mic-int {
rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
max98357a {
sdmode_en: sdmode-en {
rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pcie {
pcie_clkreqn_cpm: pci-clkreqn-cpm {
/*
* Since our pcie doesn't support ClockPM(CPM), we want
* to hack this as gpio, so the EP could be able to
* de-assert it along and make ClockPM(CPM) work.
*/
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
/*
* We run sdmmc at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
};
/*
* In our case the official card detect is hooked to ground
* to avoid getting access to JTAG just by sticking something
* in the SD card slot (see the force_jtag bit in the TRM).
*
* We still configure it as card detect because it doesn't
* hurt and dw_mmc will ignore it. We make sure to disable
* the pull though so we don't burn needless power.
*/
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 7 RK_FUNC_1 &pcfg_pull_none>;
};
/* This is where we actually hook up CD; has external pull */
sdmmc_cd_gpio: sdmmc-cd-gpio {
rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
spi1 {
spi1_sleep: spi1-sleep {
/*
* Pull down SPI1 CLK/CS/RX/TX during suspend, to
* prevent leakage.
*/
rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
<1 10 RK_FUNC_GPIO &pcfg_pull_down>,
<1 7 RK_FUNC_GPIO &pcfg_pull_down>,
<1 8 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
touchscreen {
touch_int_l: touch-int-l {
rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
};
touch_reset_l: touch-reset-l {
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
trackpad {
ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
};
trackpad_int_l: trackpad-int-l {
rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi: wifi {
wlan_module_reset_l: wlan-module-reset-l {
rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
/* Kevin has an external pull up, but Gru does not */
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
write-protect {
ap_fw_wp: ap-fw-wp {
rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
arch/arm/dts/rk3399-op1-opp.dtsi 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/ {
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <825000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <900000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <975000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1100000>;
};
opp06 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1150000>;
};
};
cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <825000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <850000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <900000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <975000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1050000>;
};
opp07 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1150000>;
};
opp08 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <1250000>;
};
};
gpu_opp_table: opp-table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <800000>;
};
opp01 {
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <825000>;
};
opp03 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <850000>;
};
opp04 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <925000>;
};
opp05 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1075000>;
};
};
};
&cpu_l0 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l1 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l2 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l3 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_b0 {
operating-points-v2 = <&cluster1_opp>;
};
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
arch/arm/dts/rk3399.dtsi
浏览文件 @ e5fd39c8
......@@ -349,45 +349,105 @@
status = "disabled";
};
dwc3_typec0: usb@fe800000 {
compatible = "rockchip,rk3399-xhci";
reg = <0x0 0xfe800000 0x0 0x100000>;
usbdrd3_0: dwc3_typec0: usb@fe800000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "aclk_usb3_rksoc_axi_perf",
"aclk_usb3", "grf_clk";
resets = <&cru SRST_A_USB3_OTG0>;
reset-names = "usb3-otg";
status = "disabled";
snps,dis-enblslpm-quirk;
snps,phyif-utmi-bits = <16>;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-u2-susphy-quirk;
usbdrd_dwc3_0: dwc3 {
compatible = "snps,dwc3";
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
phys = <&u2phy0_otg>, <&tcphy0_usb3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
};
};
dwc3_typec1: usbdrd3_1: usb@fe900000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
#size-cells = <2>;
hub {
compatible = "usb-hub";
usb,device-class = <USB_CLASS_HUB>;
};
typec_phy0 {
compatible = "rockchip,rk3399-usb3-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
ranges;
clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "aclk_usb3_rksoc_axi_perf",
"aclk_usb3", "grf_clk";
resets = <&cru SRST_A_USB3_OTG1>;
reset-names = "usb3-otg";
status = "disabled";
usbdrd_dwc3_1: dwc3 {
compatible = "snps,dwc3";
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
phys = <&u2phy1_otg>, <&tcphy1_usb3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
};
};
dwc3_typec1: usb@fe900000 {
compatible = "rockchip,rk3399-xhci";
reg = <0x0 0xfe900000 0x0 0x100000>;
cdn_dp: dp@fec00000 {
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
assigned-clock-rates = <100000000>, <200000000>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
phys = <&tcphy0_dp>, <&tcphy1_dp>;
power-domains = <&power RK3399_PD_HDCP>;
resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
<&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
reset-names = "spdif", "dptx", "apb", "core";
rockchip,grf = <&grf>;
#sound-dai-cells = <1>;
status = "disabled";
snps,dis-enblslpm-quirk;
snps,phyif-utmi-bits = <16>;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-u2-susphy-quirk;
#address-cells = <2>;
#size-cells = <2>;
hub {
compatible = "usb-hub";
usb,device-class = <USB_CLASS_HUB>;
};
typec_phy1 {
compatible = "rockchip,rk3399-usb3-phy";
reg = <0x0 0xff800000 0x0 0x40000>;
ports {
dp_in: port {
#address-cells = <1>;
#size-cells = <0>;
dp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dp>;
};
dp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dp>;
};
};
};
};
......@@ -1054,6 +1114,21 @@
status = "disabled";
};
i2c0: i2c@ff3c0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3c0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@ff3d0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3d0000 0x0 0x1000>;
......@@ -1217,7 +1292,10 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
......@@ -1225,7 +1303,10 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>;
<100000000>, <50000000>,
<400000000>, <400000000>,
<200000000>,
<200000000>;
};
grf: syscon@ff770000 {
......@@ -1314,6 +1395,56 @@
};
};
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clock-rates = <50000000>;
power-domains = <&power RK3399_PD_TCPD0>;
resets = <&cru SRST_UPHY0>,
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,grf = <&grf>;
status = "disabled";
tcphy0_dp: dp-port {
#phy-cells = <0>;
};
tcphy0_usb3: usb3-port {
#phy-cells = <0>;
};
};
tcphy1: phy@ff800000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff800000 0x0 0x40000>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
assigned-clock-rates = <50000000>;
power-domains = <&power RK3399_PD_TCPD1>;
resets = <&cru SRST_UPHY1>,
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,grf = <&grf>;
status = "disabled";
tcphy1_dp: dp-port {
#phy-cells = <0>;
};
tcphy1_usb3: usb3-port {
#phy-cells = <0>;
};
};
watchdog@ff848000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xff848000 0x0 0x100>;
......@@ -1340,6 +1471,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
#sound-dai-cells = <0>;
status = "disabled";
};
......@@ -1355,6 +1487,7 @@
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
#sound-dai-cells = <0>;
status = "disabled";
};
......@@ -1369,6 +1502,7 @@
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
#sound-dai-cells = <0>;
status = "disabled";
};
......@@ -1381,21 +1515,7 @@
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
i2c0: i2c@ff3c0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3c0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <0>;
status = "disabled";
};
......@@ -1404,69 +1524,177 @@
compatible = "rockchip,rk3399-vop-lit";
reg = <0x0 0xff8f0000 0x0 0x3efc>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
assigned-clock-rates = <400000000>, <100000000>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
iommus = <&vopl_mmu>;
power-domains = <&power RK3399_PD_VOPL>;
resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopl_out_mipi: endpoint@0 {
reg = <3>;
reg = <0>;
remote-endpoint = <&mipi_in_vopl>;
};
vopl_out_hdmi: endpoint@1 {
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
};
vopl_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
vopl_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopl>;
};
vopl_out_dp: endpoint@4 {
reg = <4>;
remote-endpoint = <&dp_in_vopl>;
};
};
};
vopl_mmu: iommu@ff8f3f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPL>;
#iommu-cells = <0>;
status = "disabled";
};
vopb: vop@ff900000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-vop-big";
reg = <0x0 0xff900000 0x0 0x3efc>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
assigned-clock-rates = <400000000>, <100000000>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
#clock-cells = <0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
iommus = <&vopb_mmu>;
power-domains = <&power RK3399_PD_VOPB>;
resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_mipi: endpoint@0 {
reg = <3>;
remote-endpoint = <&mipi_in_vopb>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_hdmi: endpoint@1 {
vopb_out_mipi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopb>;
};
vopb_out_dp: endpoint@4 {
reg = <4>;
remote-endpoint = <&dp_in_vopb>;
};
};
};
vopb_mmu: iommu@ff903f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff903f00 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPB>;
#iommu-cells = <0>;
status = "disabled";
};
isp0_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
hdmi_sound: hdmi-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "hdmi-sound";
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_SFR>,
<&cru PLL_VPLL>,
<&cru PCLK_VIO_GRF>,
<&cru SCLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "vpll", "grf", "cec";
power-domains = <&power RK3399_PD_HDCP>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_i2c_xfer>;
power-domains = <&power RK3399_PD_HDCP>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
clock-names = "iahb", "isfr", "vpll", "grf";
#sound-dai-cells = <0>;
status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
......@@ -1507,6 +1735,88 @@
};
};
mipi_dsi1: mipi@ff968000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff968000 0x0 0x8000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
clock-names = "ref", "pclk", "phy_cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
resets = <&cru SRST_P_MIPI_DSI1>;
reset-names = "apb";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi1_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi1>;
};
mipi1_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi1>;
};
};
};
};
edp: edp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
clock-names = "dp", "pclk", "grf";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
power-domains = <&power RK3399_PD_EDP>;
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "dp";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
};
};
gpu: gpu@ff9a0000 {
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
reg = <0x0 0xff9a0000 0x0 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "gpu", "job", "mmu";
clocks = <&cru ACLK_GPU>;
power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
pinctrl: pinctrl {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pinctrl";
......@@ -1911,7 +2221,7 @@
<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_cd: sdmcc-cd {
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
};
......
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
浏览文件 @ e5fd39c8
......@@ -75,6 +75,14 @@ enum {
MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
};
/* CRU_CLKSEL8_CON */
enum {
I2S0_FRAC_DENOM_SHIFT = 0,
I2S0_FRAC_DENOM_MASK = 0xffff << I2S0_FRAC_DENOM_SHIFT,
I2S0_FRAC_NUMER_SHIFT = 16,
I2S0_FRAC_NUMER_MASK = 0xffffu << I2S0_FRAC_NUMER_SHIFT,
};
/* CRU_CLKSEL12_CON */
enum {
EMMC_PLL_SHIFT = 0xe,
......
arch/arm/include/asm/arch-rockchip/gpio.h
浏览文件 @ e5fd39c8
......@@ -24,4 +24,34 @@ struct rockchip_gpio_regs {
};
check_member(rockchip_gpio_regs, ls_sync, 0x60);
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
GPIO_PULL_UP,
GPIO_PULL_DOWN,
GPIO_PULL_REPEAT,
};
/* These defines are only used by spl_gpio.h */
enum {
/* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */
GPIO_BANK_SHIFT = 3,
GPIO_BANK_MASK = 3 << GPIO_BANK_SHIFT,
GPIO_OFFSET_MASK = 0x1f,
};
#define GPIO(bank, offset) ((bank) << GPIO_BANK_SHIFT | (offset))
enum gpio_bank_t {
BANK_A = 0,
BANK_B,
BANK_C,
BANK_D,
};
enum gpio_dir_t {
GPIO_INPUT = 0,
GPIO_OUTPUT,
};
#endif
arch/arm/include/asm/arch-rockchip/grf_rk3288.h
浏览文件 @ e5fd39c8
......@@ -561,6 +561,49 @@ enum {
GPIO5C0_TS0_SYNC,
};
/* GRF_GPIO6A_IOMUX */
enum {
GPIO6A7_SHIFT = 0xe,
GPIO6A7_MASK = 1,
GPIO6A7_GPIO = 0,
GPIO6A7_I2S_SDO3,
GPIO6A6_SHIFT = 0xc,
GPIO6A6_MASK = 1,
GPIO6A6_GPIO = 0,
GPIO6A6_I2S_SDO2,
GPIO6A5_SHIFT = 0xa,
GPIO6A5_MASK = 1,
GPIO6A5_GPIO = 0,
GPIO6A5_I2S_SDO1,
GPIO6A4_SHIFT = 8,
GPIO6A4_MASK = 1,
GPIO6A4_GPIO = 0,
GPIO6A4_I2S_SDO0,
GPIO6A3_SHIFT = 6,
GPIO6A3_MASK = 1,
GPIO6A3_GPIO = 0,
GPIO6A3_I2S_SDI,
GPIO6A2_SHIFT = 4,
GPIO6A2_MASK = 1,
GPIO6A2_GPIO = 0,
GPIO6A2_I2S_LRCKTX,
GPIO6A1_SHIFT = 2,
GPIO6A1_MASK = 1,
GPIO6A1_GPIO = 0,
GPIO6A1_I2S_LRCKRX,
GPIO6A0_SHIFT = 0,
GPIO6A0_MASK = 1,
GPIO6A0_GPIO = 0,
GPIO6A0_I2S_SCLK,
};
/* GRF_GPIO6B_IOMUX */
enum {
GPIO6B3_SHIFT = 6,
......@@ -1042,6 +1085,59 @@ enum GRF_SOC_CON8 {
RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
};
/* GRF_IO_VSEL */
enum {
GPIO1830_V18SEL_SHIFT = 9,
GPIO1830_V18SEL_MASK = 1,
GPIO1830_V18SEL_3_3V = 0,
GPIO1830_V18SEL_1_8V,
GPIO30_V18SEL_SHIFT = 8,
GPIO30_V18SEL_MASK = 1,
GPIO30_V18SEL_3_3V = 0,
GPIO30_V18SEL_1_8V,
SDCARD_V18SEL_SHIFT = 7,
SDCARD_V18SEL_MASK = 1,
SDCARD_V18SEL_3_3V = 0,
SDCARD_V18SEL_1_8V,
AUDIO_V18SEL_SHIFT = 6,
AUDIO_V18SEL_MASK = 1,
AUDIO_V18SEL_3_3V = 0,
AUDIO_V18SEL_1_8V,
BB_V18SEL_SHIFT = 5,
BB_V18SEL_MASK = 1,
BB_V18SEL_3_3V = 0,
BB_V18SEL_1_8V,
WIFI_V18SEL_SHIFT = 4,
WIFI_V18SEL_MASK = 1,
WIFI_V18SEL_3_3V = 0,
WIFI_V18SEL_1_8V,
FLASH1_V18SEL_SHIFT = 3,
FLASH1_V18SEL_MASK = 1,
FLASH1_V18SEL_3_3V = 0,
FLASH1_V18SEL_1_8V,
FLASH0_V18SEL_SHIFT = 2,
FLASH0_V18SEL_MASK = 1,
FLASH0_V18SEL_3_3V = 0,
FLASH0_V18SEL_1_8V,
DVP_V18SEL_SHIFT = 1,
DVP_V18SEL_MASK = 1,
DVP_V18SEL_3_3V = 0,
DVP_V18SEL_1_8V,
LCDC_V18SEL_SHIFT = 0,
LCDC_V18SEL_MASK = 1,
LCDC_V18SEL_3_3V = 0,
LCDC_V18SEL_1_8V,
};
/* GPIO Bias settings */
enum GPIO_BIAS {
GPIO_BIAS_2MA = 0,
......@@ -1053,13 +1149,6 @@ enum GPIO_BIAS {
#define GPIO_BIAS_MASK 0x3
#define GPIO_BIAS_SHIFT(x) ((x) * 2)
enum GPIO_PU_PD {
GPIO_PULL_NORMAL = 0,
GPIO_PULL_UP,
GPIO_PULL_DOWN,
GPIO_PULL_REPEAT,
};
#define GPIO_PULL_MASK 0x3
#define GPIO_PULL_SHIFT(x) ((x) * 2)
......
arch/arm/include/asm/arch-rockchip/periph.h
浏览文件 @ e5fd39c8
......@@ -45,6 +45,7 @@ enum periph_id {
PERIPH_ID_HDMI,
PERIPH_ID_GMAC,
PERIPH_ID_SFC,
PERIPH_ID_I2S,
PERIPH_ID_COUNT,
......
arch/arm/include/asm/arch-rockchip/sys_proto.h
浏览文件 @ e5fd39c8
......@@ -29,4 +29,7 @@ static void configure_l2ctlr(void)
}
#endif /* CONFIG_ROCKCHIP_RK3288 */
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i);
#endif /* _ASM_ARCH_SYS_PROTO_H */
arch/arm/mach-rockchip/Kconfig
浏览文件 @ e5fd39c8
......@@ -29,7 +29,6 @@ config ROCKCHIP_RK3188
select SUPPORT_SPL
select SPL
select SPL_CLK
select SPL_PINCTRL
select SPL_REGMAP
select SPL_SYSCON
select SPL_RAM
......
arch/arm/mach-rockchip/boot_mode.c
浏览文件 @ e5fd39c8
......@@ -61,7 +61,13 @@ int setup_boot_mode(void)
void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG;
int boot_mode = readl(reg);
rockchip_dnl_mode_check();
/*
* This should be handled using a driver-tree property and a suitable
* driver which can read the appropriate settings. As it is, this
* breaks chromebook_minnie.\
*
* rockchip_dnl_mode_check();
*/
boot_mode = readl(reg);
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
......
arch/arm/mach-rockchip/rk3036-board.c
浏览文件 @ e5fd39c8
......@@ -7,13 +7,13 @@
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/grf_rk3036.h>
#include <asm/arch/boot_mode.h>
#include <asm/arch/sdram_rk3036.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
......
arch/arm/mach-rockchip/rk3188-board-spl.c
浏览文件 @ e5fd39c8
......@@ -12,6 +12,7 @@
#include <malloc.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
......@@ -27,7 +28,6 @@
#include <dm/test.h>
#include <dm/util.h>
#include <power/regulator.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -120,7 +120,7 @@ void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev;
struct udevice *dev;
int ret;
#define EARLY_UART
......@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
printch('s');
printch('p');
printch('l');
printch('\n');
printascii("U-Boot SPL board init");
#endif
#ifdef CONFIG_ROCKCHIP_USB_UART
......@@ -171,12 +168,6 @@ void board_init_f(ulong dummy)
return;
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("Pinctrl init failed: %d\n", ret);
return;
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
......@@ -214,7 +205,6 @@ static int setup_led(void)
void spl_board_init(void)
{
struct udevice *pinctrl;
int ret;
ret = setup_led();
......@@ -223,36 +213,9 @@ void spl_board_init(void)
hang();
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
goto err;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
if (ret) {
debug("%s: Failed to set up SD card\n", __func__);
goto err;
}
#endif
/* Enable debug UART */
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
if (ret) {
debug("%s: Failed to set up console UART\n", __func__);
goto err;
}
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
err:
printf("spl_board_init: Error %d\n", ret);
/* No way to report error here */
hang();
}
arch/arm/mach-rockchip/rk3188-board.c
浏览文件 @ e5fd39c8
......@@ -8,13 +8,13 @@
#include <dm.h>
#include <ram.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3188.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
__weak int rk_board_late_init(void)
......
arch/arm/mach-rockchip/rk322x-board.c
浏览文件 @ e5fd39c8
......@@ -8,10 +8,10 @@
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/boot_mode.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/grf_rk322x.h>
#include <asm/arch/boot_mode.h>
DECLARE_GLOBAL_DATA_PTR;
......
arch/arm/mach-rockchip/rk3288-board-spl.c
浏览文件 @ e5fd39c8
......@@ -71,51 +71,13 @@ u32 spl_boot_device(void)
fallback:
#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_MMC1;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
static int configure_emmc(struct udevice *pinctrl)
{
#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
struct gpio_desc desc;
int ret;
pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
/*
* TODO(sjg@chromium.org): Pick this up from device tree or perhaps
* use the EMMC_PWREN setting.
*/
ret = dm_gpio_lookup_name("D9", &desc);
if (ret) {
debug("gpio ret=%d\n", ret);
return ret;
}
ret = dm_gpio_request(&desc, "emmc_pwren");
if (ret) {
debug("gpio_request ret=%d\n", ret);
return ret;
}
ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
if (ret) {
debug("gpio dir ret=%d\n", ret);
return ret;
}
ret = dm_gpio_set_value(&desc, 1);
if (ret) {
debug("gpio value ret=%d\n", ret);
return ret;
}
#endif
return 0;
}
#endif
#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
......@@ -144,7 +106,6 @@ static int phycore_init(void)
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
int ret;
......@@ -183,12 +144,6 @@ void board_init_f(ulong dummy)
return;
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("Pinctrl init failed: %d\n", ret);
return;
}
#if !defined(CONFIG_SPL_OF_PLATDATA)
if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
ret = phycore_init();
......@@ -239,52 +194,19 @@ static int setup_led(void)
void spl_board_init(void)
{
struct udevice *pinctrl;
int ret;
ret = setup_led();
if (ret) {
debug("LED ret=%d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
goto err;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
if (ret) {
debug("%s: Failed to set up SD card\n", __func__);
goto err;
}
ret = configure_emmc(pinctrl);
if (ret) {
debug("%s: Failed to set up eMMC\n", __func__);
goto err;
}
#endif
/* Enable debug UART */
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
if (ret) {
debug("%s: Failed to set up console UART\n", __func__);
goto err;
}
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
err:
printf("spl_board_init: Error %d\n", ret);
/* No way to report error here */
hang();
}
#ifdef CONFIG_SPL_OS_BOOT
......
arch/arm/mach-rockchip/rk3288/Kconfig
浏览文件 @ e5fd39c8
......@@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE
functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
internal MMC. The product name is ASUS Chromebook Flip.
config TARGET_CHROMEBOOK_SPEEDY
bool "Google/Rockchip Veyron-Speedy Chromebook"
select BOARD_LATE_INIT
help
Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
micro HDMI, an 11.6 inch display, micro-SD card,
HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
EC (Cortex-M3) to provide access to the keyboard and battery
functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
The product name is Asus Chromebook C201PA.
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select BOARD_LATE_INIT
......
arch/arm/mach-rockchip/rk3368-board-spl.c
浏览文件 @ e5fd39c8
......@@ -6,7 +6,6 @@
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
......@@ -15,6 +14,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/timer.h>
#include <dm/pinctrl.h>
void board_debug_uart_init(void)
{
......
arch/arm/mach-rockchip/rk3368-board-tpl.c
浏览文件 @ e5fd39c8
......@@ -4,18 +4,18 @@
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3368.h>
#include <asm/arch/grf_rk3368.h>
#include <asm/arch/hardware.h>
#include <asm/arch/timer.h>
#include <syscon.h>
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
......
arch/arm/mach-rockchip/rk3399-board-spl.c
浏览文件 @ e5fd39c8
......@@ -5,18 +5,20 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <spl_gpio.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/io.h>
#include <debug_uart.h>
#include <dm.h>
#include <asm/arch/sys_proto.h>
#include <dm/pinctrl.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
void board_return_to_bootrom(void)
{
......@@ -128,7 +130,13 @@ void secure_timer_init(void)
void board_debug_uart_init(void)
{
#define GRF_BASE 0xff770000
#define GPIO0_BASE 0xff720000
#define PMUGRF_BASE 0xff320000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
#endif
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
......@@ -139,6 +147,20 @@ void board_debug_uart_init(void)
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
#else
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
rk_setreg(&grf->io_vsel, 1 << 0);
/*
* Let's enable these power rails here, we are already running the SPI
* Flash based code.
*/
spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
......@@ -163,6 +185,22 @@ void board_init_f(ulong dummy)
#define EARLY_UART
#ifdef EARLY_UART
debug_uart_init();
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
int sum, i;
/*
* Add a delay and ensure that the compiler does not optimise this out.
* This is needed since the power rails tail a while to turn on, and
* we get garbage serial output otherwise.
*/
sum = 0;
for (i = 0; i < 150000; i++)
sum += i;
gru_dummy_function(sum);
#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
/*
* Debug UART can be used from here if required:
*
......@@ -171,7 +209,6 @@ void board_init_f(ulong dummy)
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("U-Boot SPL board init\n");
#endif
......
arch/arm/mach-rockchip/rk3399/Kconfig
浏览文件 @ e5fd39c8
......@@ -53,6 +53,15 @@ config TARGET_ROCK960_RK3399
* 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only),
1x USB 3.0 type C OTG
config TARGET_CHROMEBOOK_BOB
bool "Asus Flip C101PA Chromebook (RK3399)"
help
Bob is a small RK3299-based device similar in apperance to Minnie.
It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1",
1280x800 display. It uses its USB ports for both power and external
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
endchoice
config SYS_SOC
......@@ -64,5 +73,6 @@ config SYS_MALLOC_F_LEN
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
source "board/google/gru/Kconfig"
endif
arch/arm/mach-rockchip/spl-boot-order.c
浏览文件 @ e5fd39c8
......@@ -61,6 +61,9 @@ static int spl_node_to_boot_device(int node)
default:
return -ENOSYS;
}
} else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
&parent)) {
return BOOT_DEVICE_SPI;
}
/*
......
board/google/gru/Kconfig 0 → 100644
浏览文件 @ e5fd39c8
if TARGET_CHROMEBOOK_BOB
config SYS_BOARD
default "gru"
config SYS_VENDOR
default "google"
config SYS_CONFIG_NAME
default "gru"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
board/google/gru/MAINTAINERS 0 → 100644
浏览文件 @ e5fd39c8
CHROMEBOOK BOB BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_bob_defconfig
board/google/gru/Makefile 0 → 100644
浏览文件 @ e5fd39c8
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2019 Google LLC
obj-y += gru.o
board/google/gru/gru.c 0 → 100644
浏览文件 @ e5fd39c8
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Google
*/
#include <common.h>
int board_init(void)
{
return 0;
}
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i)
{
}
board/google/veyron/Kconfig
浏览文件 @ e5fd39c8
......@@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBOOK_SPEEDY
config SYS_BOARD
default "veyron"
config SYS_VENDOR
default "google"
config SYS_CONFIG_NAME
default "veyron"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
board/google/veyron/MAINTAINERS
浏览文件 @ e5fd39c8
......@@ -18,3 +18,10 @@ S: Maintained
F: board/google/veyron/
F: include/configs/veyron.h
F: configs/chromebook_minnie_defconfig
CHROMEBOOK SPEEDY BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/google/veyron/
F: include/configs/veyron.h
F: configs/chromebook_speedy_defconfig
board/rockchip/evb_rk3399/README
浏览文件 @ e5fd39c8
......@@ -35,21 +35,29 @@ Get the Source and prebuild binary
> git clone https://github.com/rockchip-linux/rkbin.git
> git clone https://github.com/rockchip-linux/rkdeveloptool.git
Compile the ATF
===============
Get some prerequisites
======================
You need the Python elftools.elf.elffile library for make_fit_atf.py to work:
> sudo apt-get install python-pyelftools
Compile ATF
===========
> cd arm-trusted-firmware
> make realclean
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
Get bl31.elf in this step, copy it to U-Boot root dir:
> cp build/rk3399/release/bl31/bl31.elf ../u-boot/
Or you can get the bl31.elf directly from Rockchip:
cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf
> cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf
Get bl31.elf in this step, copy it to U-Boot root dir:
> cp bl31.elf ../u-boot/
Compile the U-Boot
==================
Compile U-Boot
==============
> cd ../u-boot
> export ARCH=arm64
......@@ -62,17 +70,18 @@ Compile the U-Boot
Get spl/u-boot-spl.bin and u-boot.itb in this step.
Compile the rkdeveloptool
=======================
Follow instructions in latest README
Compile rkdeveloptool
=====================
Get rkdeveloptool installed on your Host in this step.
Follow instructions in latest README, example:
> cd ../rkdeveloptool
> autoreconf -i
> ./configure
> make
> sudo make install
Get rkdeveloptool in you Host in this step.
Both origin binaries and Tool are ready now, choose either option 1 or
option 2 to deploy U-Boot.
......
cmd/gpio.c
浏览文件 @ e5fd39c8
......@@ -18,10 +18,10 @@ __weak int name_to_gpio(const char *name)
}
enum gpio_cmd {
GPIO_INPUT,
GPIO_SET,
GPIO_CLEAR,
GPIO_TOGGLE,
GPIOC_INPUT,
GPIOC_SET,
GPIOC_CLEAR,
GPIOC_TOGGLE,
};
#if defined(CONFIG_DM_GPIO) && !defined(gpio_status)
......@@ -158,11 +158,20 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* parse the behavior */
switch (*str_cmd) {
case 'i': sub_cmd = GPIO_INPUT; break;
case 's': sub_cmd = GPIO_SET; break;
case 'c': sub_cmd = GPIO_CLEAR; break;
case 't': sub_cmd = GPIO_TOGGLE; break;
default: goto show_usage;
case 'i':
sub_cmd = GPIOC_INPUT;
break;
case 's':
sub_cmd = GPIOC_SET;
break;
case 'c':
sub_cmd = GPIOC_CLEAR;
break;
case 't':
sub_cmd = GPIOC_TOGGLE;
break;
default:
goto show_usage;
}
#if defined(CONFIG_DM_GPIO)
......@@ -192,18 +201,18 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
/* finally, let's do it: set direction and exec command */
if (sub_cmd == GPIO_INPUT) {
if (sub_cmd == GPIOC_INPUT) {
gpio_direction_input(gpio);
value = gpio_get_value(gpio);
} else {
switch (sub_cmd) {
case GPIO_SET:
case GPIOC_SET:
value = 1;
break;
case GPIO_CLEAR:
case GPIOC_CLEAR:
value = 0;
break;
case GPIO_TOGGLE:
case GPIOC_TOGGLE:
value = gpio_get_value(gpio);
if (!IS_ERR_VALUE(value))
value = !value;
......@@ -218,7 +227,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("unknown (ret=%d)\n", value);
else
printf("%d\n", value);
if (sub_cmd != GPIO_INPUT && !IS_ERR_VALUE(value)) {
if (sub_cmd != GPIOC_INPUT && !IS_ERR_VALUE(value)) {
int nval = gpio_get_value(gpio);
if (IS_ERR_VALUE(nval))
......
configs/chromebit_mickey_defconfig
浏览文件 @ e5fd39c8
......@@ -38,7 +38,6 @@ CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
......@@ -62,8 +61,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
......@@ -92,4 +89,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_OF_LIBFDT is not set
configs/chromebook_bob_defconfig 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
configs/chromebook_jerry_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/chromebook_minnie_defconfig
浏览文件 @ e5fd39c8
......@@ -39,7 +39,6 @@ CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
......@@ -63,8 +62,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
......@@ -94,4 +91,3 @@ CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_OF_LIBFDT is not set
configs/chromebook_speedy_defconfig 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
configs/evb-px5_defconfig
浏览文件 @ e5fd39c8
......@@ -22,7 +22,6 @@ CONFIG_CLK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
......
configs/evb-rk3128_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/evb-rk3229_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/evb-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/evb-rk3399_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/evb-rv1108_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/fennec-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/firefly-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/firefly-rk3399_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/geekbox_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/kylin-rk3036_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/kylin-rk3036_defconfig.rej 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
configs/lion-rk3368_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/miqi-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/phycore-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/popmetal-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/puma-rk3399_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/puma-rk3399_defconfig.rej 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
configs/rock2_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/rock_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/sandbox_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/sandbox_flattree_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/sandbox_noblk_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/sheep-rk3368_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/tinker-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
configs/vyasa-rk3288_defconfig
浏览文件 @ e5fd39c8
此差异已折叠。
doc/README.rockchip
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/clk/clk-uclass.c
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/clk/rockchip/clk_rk3288.c
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/clk/rockchip/clk_rk3399.c
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/gpio/rk_gpio.c
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/Kconfig
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/Makefile
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/Kconfig 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/Makefile
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3036.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3128.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3188.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk322x.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3288.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3328.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3368.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rk3399.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rockchip.h 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl-rv1108.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3036.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3128.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3188.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk322x.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3288.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3328.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3368.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rk3399.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/pinctrl/rockchip/pinctrl_rv1108.c 已删除 100644 → 0
浏览文件 @ 544d5e98
此差异已折叠。
drivers/sound/Kconfig
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/sound/Makefile
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/sound/rockchip_i2s.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
drivers/sound/rockchip_sound.c 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
include/configs/gru.h 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
include/configs/rk3399_common.h
浏览文件 @ e5fd39c8
此差异已折叠。
include/spl_gpio.h 0 → 100644
浏览文件 @ e5fd39c8
此差异已折叠。
lib/display_options.c
浏览文件 @ e5fd39c8
此差异已折叠。
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或