Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips

- MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
- MIPS: mt76xx: fix timer frequency

MAINTAINERS

@@ -561,7 +561,7 @@ F:	drivers/gpio/mscc_sgpio.c
 F:	drivers/spi/mscc_bb_spi.c
 F:	include/configs/vcoreiii.h
 F:	drivers/pinctrl/mscc/
-F:	drivers/net/ocelot_switch.c
+F:	drivers/net/mscc_eswitch/
 
 MIPS JZ4780
 M:	Ezequiel Garcia <ezequiel@collabora.com>

arch/mips/dts/luton_pcb090.dts

@@ -55,3 +55,54 @@
 	};
 };
 
+&mdio0 {
+	status = "okay";
+};
+
+&port0 {
+	phy-handle = <&phy0>;
+};
+
+&port1 {
+	phy-handle = <&phy1>;
+};
+
+&port2 {
+	phy-handle = <&phy2>;
+};
+
+&port3 {
+	phy-handle = <&phy3>;
+};
+
+&port4 {
+	phy-handle = <&phy4>;
+};
+
+&port5 {
+	phy-handle = <&phy5>;
+};
+
+&port6 {
+	phy-handle = <&phy6>;
+};
+
+&port7 {
+	phy-handle = <&phy7>;
+};
+
+&port8 {
+	phy-handle = <&phy8>;
+};
+
+&port9 {
+	phy-handle = <&phy9>;
+};
+
+&port10 {
+	phy-handle = <&phy10>;
+};
+
+&port11 {
+	phy-handle = <&phy11>;
+};

arch/mips/dts/luton_pcb091.dts

@@ -61,3 +61,54 @@
 	};
 };
 
+&mdio0 {
+	status = "okay";
+};
+
+&port0 {
+	phy-handle = <&phy0>;
+};
+
+&port1 {
+	phy-handle = <&phy1>;
+};
+
+&port2 {
+	phy-handle = <&phy2>;
+};
+
+&port3 {
+	phy-handle = <&phy3>;
+};
+
+&port4 {
+	phy-handle = <&phy4>;
+};
+
+&port5 {
+	phy-handle = <&phy5>;
+};
+
+&port6 {
+	phy-handle = <&phy6>;
+};
+
+&port7 {
+	phy-handle = <&phy7>;
+};
+
+&port8 {
+	phy-handle = <&phy8>;
+};
+
+&port9 {
+	phy-handle = <&phy9>;
+};
+
+&port10 {
+	phy-handle = <&phy10>;
+};
+
+&port11 {
+	phy-handle = <&phy11>;
+};

arch/mips/dts/mscc,luton.dtsi

@@ -92,5 +92,170 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
+
+		switch: switch@1010000 {
+			compatible = "mscc,vsc7527-switch";
+			reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
+			      <0x1f0000 0x0100>, // VTSS_TO_DEV_1
+			      <0x200000 0x0100>, // VTSS_TO_DEV_2
+			      <0x210000 0x0100>, // VTSS_TO_DEV_3
+			      <0x220000 0x0100>, // VTSS_TO_DEV_4
+			      <0x230000 0x0100>, // VTSS_TO_DEV_5
+			      <0x240000 0x0100>, // VTSS_TO_DEV_6
+			      <0x250000 0x0100>, // VTSS_TO_DEV_7
+			      <0x260000 0x0100>, // VTSS_TO_DEV_8
+			      <0x270000 0x0100>, // VTSS_TO_DEV_9
+			      <0x280000 0x0100>, // VTSS_TO_DEV_10
+			      <0x290000 0x0100>, // VTSS_TO_DEV_11
+			      <0x2a0000 0x0100>, // VTSS_TO_DEV_12
+			      <0x2b0000 0x0100>, // VTSS_TO_DEV_13
+			      <0x2c0000 0x0100>, // VTSS_TO_DEV_14
+			      <0x2d0000 0x0100>, // VTSS_TO_DEV_15
+			      <0x2e0000 0x0100>, // VTSS_TO_DEV_16
+			      <0x2f0000 0x0100>, // VTSS_TO_DEV_17
+			      <0x300000 0x0100>, // VTSS_TO_DEV_18
+			      <0x310000 0x0100>, // VTSS_TO_DEV_19
+			      <0x320000 0x0100>, // VTSS_TO_DEV_20
+			      <0x330000 0x0100>, // VTSS_TO_DEV_21
+			      <0x340000 0x0100>, // VTSS_TO_DEV_22
+			      <0x350000 0x0100>, // VTSS_TO_DEV_23
+			      <0x010000 0x1000>, // VTSS_TO_SYS
+			      <0x020000 0x1000>, // VTSS_TO_ANA
+			      <0x030000 0x1000>, // VTSS_TO_REW
+			      <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
+			      <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
+			      <0x0a0000 0x0100>; // VTSS_TO_HSIO
+			reg-names = "port0", "port1", "port2", "port3",
+				    "port4", "port5", "port6", "port7",
+				    "port8", "port9", "port10", "port11",
+				    "port12", "port13", "port14", "port15",
+				    "port16", "port17", "port18", "port19",
+				    "port20", "port21", "port22", "port23",
+				    "sys", "ana", "rew", "gcb", "qs", "hsio";
+			status = "okay";
+
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port0: port@0 {
+					reg = <0>;
+				};
+				port1: port@1 {
+					reg = <1>;
+				};
+				port2: port@2 {
+					reg = <2>;
+				};
+				port3: port@3 {
+					reg = <3>;
+				};
+				port4: port@4 {
+					reg = <4>;
+				};
+				port5: port@5 {
+					reg = <5>;
+				};
+				port6: port@6 {
+					reg = <6>;
+				};
+				port7: port@7 {
+					reg = <7>;
+				};
+				port8: port@8 {
+					reg = <8>;
+				};
+				port9: port@9 {
+					reg = <9>;
+				};
+				port10: port@10 {
+					reg = <10>;
+				};
+				port11: port@11 {
+					reg = <11>;
+				};
+				port12: port@12 {
+					reg = <12>;
+				};
+				port13: port@13 {
+					reg = <13>;
+				};
+				port14: port@14 {
+					reg = <14>;
+				};
+				port15: port@15 {
+					reg = <15>;
+				};
+				port16: port@16 {
+					reg = <16>;
+				};
+				port17: port@17 {
+					reg = <17>;
+				};
+				port18: port@18 {
+					reg = <18>;
+				};
+				port19: port@19 {
+					reg = <19>;
+				};
+				port20: port@20 {
+					reg = <20>;
+				};
+				port21: port@21 {
+					reg = <21>;
+				};
+				port22: port@22 {
+					reg = <22>;
+				};
+				port23: port@23 {
+					reg = <23>;
+				};
+			};
+		};
+
+		mdio0: mdio@700a0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,luton-miim";
+			reg = <0x700a0 0x24>;
+			status = "disabled";
+
+			phy0: ethernet-phy@0 {
+				reg = <0>;
+			};
+			phy1: ethernet-phy@1 {
+				reg = <1>;
+			};
+			phy2: ethernet-phy@2 {
+				reg = <2>;
+			};
+			phy3: ethernet-phy@3 {
+				reg = <3>;
+			};
+			phy4: ethernet-phy@4 {
+				reg = <4>;
+			};
+			phy5: ethernet-phy@5 {
+				reg = <5>;
+			};
+			phy6: ethernet-phy@6 {
+				reg = <6>;
+			};
+			phy7: ethernet-phy@7 {
+				reg = <7>;
+			};
+			phy8: ethernet-phy@8 {
+				reg = <8>;
+			};
+			phy9: ethernet-phy@9 {
+				reg = <9>;
+			};
+			phy10: ethernet-phy@10 {
+				reg = <10>;
+			};
+			phy11: ethernet-phy@11 {
+				reg = <11>;
+			};
+		};
 	};
 };

board/mscc/jr2/jr2.c

@@ -64,6 +64,13 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode)
 	}
 }
 
+void board_debug_uart_init(void)
+{
+	/* too early for the pinctrl driver, so configure the UART pins here */
+	vcoreiii_gpio_set_alternate(10, 1);
+	vcoreiii_gpio_set_alternate(11, 1);
+}
+
 static void do_board_detect(void)
 {
 	int i;
@@ -73,6 +80,9 @@ static void do_board_detect(void)
 	for (i = 56; i < 60; i++)
 		vcoreiii_gpio_set_alternate(i, 1);
 
+	/* small delay for settling the pins */
+	mdelay(30);
+
 	if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
 	    ((pval >> 4) & 0x3F) == 0x3c) {
 		gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */

configs/mscc_jr2_defconfig

@@ -56,3 +56,9 @@ CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_LZMA=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y

configs/mscc_luton_defconfig

@@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
+CONFIG_MSCC_LUTON_SWITCH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_DM_SERIAL=y

drivers/net/Kconfig

@@ -432,12 +432,7 @@ config SNI_AVE
 	  This driver implements support for the Socionext AVE Ethernet
 	  controller, as found on the Socionext UniPhier family.
 
-config MSCC_OCELOT_SWITCH
-	bool "Ocelot switch driver"
-	depends on DM_ETH && ARCH_MSCC
-	select PHYLIB
-	help
-	  This driver supports the Ocelot network switch device.
+source "drivers/net/mscc_eswitch/Kconfig"
 
 config ETHER_ON_FEC1
 	bool "FEC1"

drivers/net/Makefile

@@ -75,4 +75,4 @@ obj-$(CONFIG_FSL_PFE) += pfe_eth/
 obj-$(CONFIG_SNI_AVE) += sni_ave.o
 obj-y += ti/
 obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
+obj-y += mscc_eswitch/

drivers/net/mscc_eswitch/Kconfig

+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Microsemi Corporation
+
+config MSCC_OCELOT_SWITCH
+	bool "Ocelot switch driver"
+	depends on DM_ETH && ARCH_MSCC
+	select PHYLIB
+	help
+	  This driver supports the Ocelot network switch device.
+
+config MSCC_LUTON_SWITCH
+	bool "Luton switch driver"
+	depends on DM_ETH && ARCH_MSCC
+	select PHYLIB
+	help
+	  This driver supports the Luton network switch device.

drivers/net/mscc_eswitch/Makefile

+
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o

drivers/net/mscc_eswitch/mscc_mac_table.c

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <linux/io.h>
+#include "mscc_mac_table.h"
+
+#define ANA_TABLES_MACACCESS_VALID		BIT(11)
+#define ANA_TABLES_MACACCESS_ENTRYTYPE(x)	((x) << 9)
+#define ANA_TABLES_MACACCESS_DEST_IDX(x)	((x) << 3)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x)	(x)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M	GENMASK(2, 0)
+#define MACACCESS_CMD_IDLE			0
+#define MACACCESS_CMD_LEARN			1
+
+/* MAC table entry types.
+ * ENTRYTYPE_NORMAL is subject to aging.
+ * ENTRYTYPE_LOCKED is not subject to aging.
+ */
+enum macaccess_entry_type {
+	ENTRYTYPE_NORMAL = 0,
+	ENTRYTYPE_LOCKED,
+};
+
+static int vlan_wait_for_completion(void __iomem *regs,
+				    const unsigned long *mscc_mac_table_offset)
+{
+	unsigned int val, timeout = 10;
+
+	/* Wait for the issued mac table command to be completed, or timeout.
+	 * When the command read from ANA_TABLES_MACACCESS is
+	 * MACACCESS_CMD_IDLE, the issued command completed successfully.
+	 */
+	do {
+		val = readl(regs +
+			    mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+		val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
+	} while (val != MACACCESS_CMD_IDLE && timeout--);
+
+	if (!timeout)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+int mscc_mac_table_add(void __iomem *regs,
+		       const unsigned long *mscc_mac_table_offset,
+		       const unsigned char mac[ETH_LEN], int pgid)
+{
+	u32 macl = 0, mach = 0;
+
+	/* Set the MAC address to handle and the vlan associated in a format
+	 * understood by the hardware.
+	 */
+	mach |= MAC_VID << 16;
+	mach |= ((u32)mac[0]) << 8;
+	mach |= ((u32)mac[1]) << 0;
+	macl |= ((u32)mac[2]) << 24;
+	macl |= ((u32)mac[3]) << 16;
+	macl |= ((u32)mac[4]) << 8;
+	macl |= ((u32)mac[5]) << 0;
+
+	writel(macl, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACLDATA]);
+	writel(mach, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACHDATA]);
+
+	writel(ANA_TABLES_MACACCESS_VALID |
+	       ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
+	       ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
+	       ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
+	       regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+
+	return vlan_wait_for_completion(regs, mscc_mac_table_offset);
+}

drivers/net/mscc_eswitch/mscc_mac_table.h

+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#define ETH_LEN 6
+#define MAC_VID 1
+
+enum mscc_regs_ana_table {
+	MSCC_ANA_TABLES_MACHDATA,
+	MSCC_ANA_TABLES_MACLDATA,
+	MSCC_ANA_TABLES_MACACCESS,
+};
+
+int mscc_mac_table_add(void __iomem *regs,
+		       const unsigned long *mscc_mac_table_offset,
+		       const unsigned char mac[ETH_LEN], int pgid);

drivers/net/mscc_eswitch/mscc_miim.c

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <miiphy.h>
+#include <wait_bit.h>
+#include "mscc_miim.h"
+
+#define MIIM_STATUS			0x0
+#define		MIIM_STAT_BUSY			BIT(3)
+#define MIIM_CMD			0x8
+#define		MIIM_CMD_SCAN		BIT(0)
+#define		MIIM_CMD_OPR_WRITE	BIT(1)
+#define		MIIM_CMD_OPR_READ	BIT(2)
+#define		MIIM_CMD_SINGLE_SCAN	BIT(3)
+#define		MIIM_CMD_WRDATA(x)	((x) << 4)
+#define		MIIM_CMD_REGAD(x)	((x) << 20)
+#define		MIIM_CMD_PHYAD(x)	((x) << 25)
+#define		MIIM_CMD_VLD		BIT(31)
+#define MIIM_DATA			0xC
+#define		MIIM_DATA_ERROR		(0x2 << 16)
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+	return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
+				 false, 250, false);
+}
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+	u32 val;
+	int ret;
+
+	ret = mscc_miim_wait_ready(miim);
+	if (ret)
+		goto out;
+
+	writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+	       MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
+	       miim->regs + MIIM_CMD);
+
+	ret = mscc_miim_wait_ready(miim);
+	if (ret)
+		goto out;
+
+	val = readl(miim->regs + MIIM_DATA);
+	if (val & MIIM_DATA_ERROR) {
+		ret = -EIO;
+		goto out;
+	}
+
+	ret = val & 0xFFFF;
+ out:
+	return ret;
+}
+
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+		    u16 val)
+{
+	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+	int ret;
+
+	ret = mscc_miim_wait_ready(miim);
+	if (ret < 0)
+		goto out;
+
+	writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+	       MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
+	       MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
+ out:
+	return ret;
+}

drivers/net/mscc_eswitch/mscc_miim.h

+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+struct mscc_miim_dev {
+	void __iomem *regs;
+	void __iomem *phy_regs;
+};
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg);
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val);

drivers/net/mscc_eswitch/mscc_xfer.c

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <linux/io.h>
+#include "mscc_xfer.h"
+
+#define QS_XTR_FLUSH_FLUSH		GENMASK(1, 0)
+#define QS_INJ_CTRL_GAP_SIZE(x)		((x) << 21)
+#define QS_INJ_CTRL_EOF			BIT(19)
+#define QS_INJ_CTRL_SOF			BIT(18)
+#define QS_INJ_CTRL_VLD_BYTES(x)	((x) << 16)
+
+#define XTR_EOF_0     ntohl(0x80000000u)
+#define XTR_EOF_1     ntohl(0x80000001u)
+#define XTR_EOF_2     ntohl(0x80000002u)
+#define XTR_EOF_3     ntohl(0x80000003u)
+#define XTR_PRUNED    ntohl(0x80000004u)
+#define XTR_ABORT     ntohl(0x80000005u)
+#define XTR_ESCAPE    ntohl(0x80000006u)
+#define XTR_NOT_READY ntohl(0x80000007u)
+
+#define BUF_CELL_SZ		60
+#define XTR_VALID_BYTES(x)	(4 - ((x) & 3))
+
+int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
+	      u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len)
+{
+	int i, count = (buff_len + 3) / 4, last = buff_len % 4;
+
+	writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
+	       regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+	for (i = 0; i < ifh_len; i++)
+		writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+	for (i = 0; i < count; i++)
+		writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+	/* Add padding */
+	while (i < (BUF_CELL_SZ / 4)) {
+		writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+		i++;
+	}
+
+	/* Indicate EOF and valid bytes in last word */
+	writel(QS_INJ_CTRL_GAP_SIZE(1) |
+	       QS_INJ_CTRL_VLD_BYTES(buff_len < BUF_CELL_SZ ? 0 : last) |
+	       QS_INJ_CTRL_EOF, regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+	/* Add dummy CRC */
+	writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+	return 0;
+}
+
+int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
+	      u32 *rxbuf, size_t ifh_len, bool byte_swap)
+{
+	u8 grp = 0; /* Recv everything on CPU group 0 */
+	int i, byte_cnt = 0;
+	bool eof_flag = false, pruned_flag = false, abort_flag = false;
+
+	if (!(readl(regs + mscc_qs_offset[MSCC_QS_XTR_DATA_PRESENT]) &
+	      BIT(grp)))
+		return -EAGAIN;
+
+	/* skip IFH */
+	for (i = 0; i < ifh_len; i++)
+		readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+
+	while (!eof_flag) {
+		u32 val = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+		u32 cmp = val;
+
+		if (byte_swap)
+			cmp = ntohl(val);
+
+		switch (cmp) {
+		case XTR_NOT_READY:
+			debug("%d NOT_READY...?\n", byte_cnt);
+			break;
+		case XTR_ABORT:
+			*rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+			abort_flag = true;
+			eof_flag = true;
+			debug("XTR_ABORT\n");
+			break;
+		case XTR_EOF_0:
+		case XTR_EOF_1:
+		case XTR_EOF_2:
+		case XTR_EOF_3:
+			byte_cnt += XTR_VALID_BYTES(val);
+			*rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+			eof_flag = true;
+			debug("EOF\n");
+			break;
+		case XTR_PRUNED:
+			/* But get the last 4 bytes as well */
+			eof_flag = true;
+			pruned_flag = true;
+			debug("PRUNED\n");
+			/* fallthrough */
+		case XTR_ESCAPE:
+			*rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+			byte_cnt += 4;
+			rxbuf++;
+			debug("ESCAPED\n");
+			break;
+		default:
+			*rxbuf = val;
+			byte_cnt += 4;
+			rxbuf++;
+		}
+	}
+
+	if (abort_flag || pruned_flag || !eof_flag) {
+		debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
+		      abort_flag, pruned_flag, eof_flag);
+		return -EAGAIN;
+	}
+
+	return byte_cnt;
+}
+
+void mscc_flush(void __iomem *regs, const unsigned long *mscc_qs_offset)
+{
+	/* All Queues flush */
+	setbits_le32(regs + mscc_qs_offset[MSCC_QS_XTR_FLUSH],
+		     QS_XTR_FLUSH_FLUSH);
+
+	/* Allow to drain */
+	mdelay(1);
+
+	/* All Queues normal */
+	clrbits_le32(regs + mscc_qs_offset[MSCC_QS_XTR_FLUSH],
+		     QS_XTR_FLUSH_FLUSH);
+}

drivers/net/mscc_eswitch/mscc_xfer.h

+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+enum mscc_regs_qs {
+	MSCC_QS_XTR_RD,
+	MSCC_QS_XTR_FLUSH,
+	MSCC_QS_XTR_DATA_PRESENT,
+	MSCC_QS_INJ_WR,
+	MSCC_QS_INJ_CTRL,
+};
+
+int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
+	      u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len);
+int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
+	      u32 *rxbuf, size_t ifh_len, bool byte_swap);
+void mscc_flush(void __iomem *regs, const unsigned long *mscc_qs_offset);

drivers/net/ocelot_switch.c → drivers/net/mscc_eswitch/ocelot_switch.c

@@ -15,19 +15,9 @@
 #include <net.h>
 #include <wait_bit.h>
 
-#define MIIM_STATUS			0x0
-#define		MIIM_STAT_BUSY			BIT(3)
-#define MIIM_CMD			0x8
-#define		MIIM_CMD_SCAN		BIT(0)
-#define		MIIM_CMD_OPR_WRITE	BIT(1)
-#define		MIIM_CMD_OPR_READ	BIT(2)
-#define		MIIM_CMD_SINGLE_SCAN	BIT(3)
-#define		MIIM_CMD_WRDATA(x)	((x) << 4)
-#define		MIIM_CMD_REGAD(x)	((x) << 20)
-#define		MIIM_CMD_PHYAD(x)	((x) << 25)
-#define		MIIM_CMD_VLD		BIT(31)
-#define MIIM_DATA			0xC
-#define		MIIM_DATA_ERROR		(0x2 << 16)
+#include "mscc_miim.h"
+#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
 
 #define PHY_CFG				0x0
 #define PHY_CFG_ENA				0xF
@@ -41,17 +31,6 @@
 #define		ANA_PORT_VLAN_CFG_POP_CNT(x)	((x) << 18)
 #define ANA_PORT_PORT_CFG(x)		(0x7070 + 0x100 * (x))
 #define		ANA_PORT_PORT_CFG_RECV_ENA	BIT(6)
-#define	ANA_TABLES_MACHDATA		0x8b34
-#define	ANA_TABLES_MACLDATA		0x8b38
-#define ANA_TABLES_MACACCESS		0x8b3c
-#define		ANA_TABLES_MACACCESS_VALID	BIT(11)
-#define		ANA_TABLES_MACACCESS_ENTRYTYPE(x)   ((x) << 9)
-#define		ANA_TABLES_MACACCESS_DEST_IDX(x)    ((x) << 3)
-#define		ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x)	(x)
-#define		ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M	GENMASK(2, 0)
-#define		MACACCESS_CMD_IDLE                     0
-#define		MACACCESS_CMD_LEARN                    1
-#define		MACACCESS_CMD_GET_NEXT                 4
 #define ANA_PGID(x)			(0x8c00 + 4 * (x))
 
 #define SYS_FRM_AGING			0x574
@@ -99,37 +78,16 @@
 #define QS_XTR_GRP_CFG_MODE(x)			((x) << 2)
 #define		QS_XTR_GRP_CFG_STATUS_WORD_POS	BIT(1)
 #define		QS_XTR_GRP_CFG_BYTE_SWAP	BIT(0)
-#define QS_XTR_RD(x)			(0x8 + 4 * (x))
-#define QS_XTR_FLUSH			0x18
-#define		QS_XTR_FLUSH_FLUSH		GENMASK(1, 0)
-#define QS_XTR_DATA_PRESENT		0x1c
 #define QS_INJ_GRP_CFG(x)		(0x24 + (x) * 4)
 #define		QS_INJ_GRP_CFG_MODE(x)		((x) << 2)
 #define		QS_INJ_GRP_CFG_BYTE_SWAP	BIT(0)
-#define QS_INJ_WR(x)			(0x2c + 4 * (x))
-#define QS_INJ_CTRL(x)			(0x34 + 4 * (x))
-#define		QS_INJ_CTRL_GAP_SIZE(x)		((x) << 21)
-#define		QS_INJ_CTRL_EOF			BIT(19)
-#define		QS_INJ_CTRL_SOF			BIT(18)
-#define		QS_INJ_CTRL_VLD_BYTES(x)	((x) << 16)
-
-#define XTR_EOF_0     ntohl(0x80000000u)
-#define XTR_EOF_1     ntohl(0x80000001u)
-#define XTR_EOF_2     ntohl(0x80000002u)
-#define XTR_EOF_3     ntohl(0x80000003u)
-#define XTR_PRUNED    ntohl(0x80000004u)
-#define XTR_ABORT     ntohl(0x80000005u)
-#define XTR_ESCAPE    ntohl(0x80000006u)
-#define XTR_NOT_READY ntohl(0x80000007u)
 
 #define IFH_INJ_BYPASS		BIT(31)
 #define	IFH_TAG_TYPE_C		0
-#define XTR_VALID_BYTES(x)	(4 - ((x) & 3))
 #define	MAC_VID			1
 #define CPU_PORT		11
 #define INTERNAL_PORT_MSK	0xF
 #define IFH_LEN			4
-#define OCELOT_BUF_CELL_SZ	60
 #define ETH_ALEN		6
 #define	PGID_BROADCAST		13
 #define	PGID_UNICAST		14
@@ -151,19 +109,6 @@ enum ocelot_target {
 
 #define MAX_PORT (PORT3 - PORT0)
 
-/* MAC table entry types.
- * ENTRYTYPE_NORMAL is subject to aging.
- * ENTRYTYPE_LOCKED is not subject to aging.
- * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
- * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
- */
-enum macaccess_entry_type {
-	ENTRYTYPE_NORMAL = 0,
-	ENTRYTYPE_LOCKED,
-	ENTRYTYPE_MACv4,
-	ENTRYTYPE_MACv6,
-};
-
 enum ocelot_mdio_target {
 	MIIM,
 	PHY,
@@ -178,33 +123,24 @@ enum ocelot_phy_id {
 
 struct ocelot_private {
 	void __iomem *regs[TARGET_MAX];
-
 	struct mii_dev *bus[NUM_PHY];
-	struct phy_device *phydev;
-	int phy_mode;
-	int max_speed;
-
-	int rx_pos;
-	int rx_siz;
-	int rx_off;
-	int tx_num;
+};
 
-	u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
-	void *tx_adj_buf;
+static const unsigned long ocelot_regs_qs[] = {
+	[MSCC_QS_XTR_RD] = 0x8,
+	[MSCC_QS_XTR_FLUSH] = 0x18,
+	[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
+	[MSCC_QS_INJ_WR] = 0x2c,
+	[MSCC_QS_INJ_CTRL] = 0x34,
 };
 
-struct mscc_miim_dev {
-	void __iomem *regs;
-	void __iomem *phy_regs;
+static const unsigned long ocelot_regs_ana_table[] = {
+	[MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
+	[MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
+	[MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
 };
 
-struct mscc_miim_dev miim[NUM_PHY];
-
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
-	return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
-				 false, 250, false);
-}
+static struct mscc_miim_dev miim[NUM_PHY];
 
 static int mscc_miim_reset(struct mii_dev *bus)
 {
@@ -220,52 +156,6 @@ static int mscc_miim_reset(struct mii_dev *bus)
 	return 0;
 }
 
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
-	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-	u32 val;
-	int ret;
-
-	ret = mscc_miim_wait_ready(miim);
-	if (ret)
-		goto out;
-
-	writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
-	       MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
-	       miim->regs + MIIM_CMD);
-
-	ret = mscc_miim_wait_ready(miim);
-	if (ret)
-		goto out;
-
-	val = readl(miim->regs + MIIM_DATA);
-	if (val & MIIM_DATA_ERROR) {
-		ret = -EIO;
-		goto out;
-	}
-
-	ret = val & 0xFFFF;
- out:
-	return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
-			   u16 val)
-{
-	struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-	int ret;
-
-	ret = mscc_miim_wait_ready(miim);
-	if (ret < 0)
-		goto out;
-
-	writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
-	       MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
-	       MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
- out:
-	return ret;
-}
-
 /* For now only setup the internal mdio bus */
 static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
 {
@@ -436,16 +326,6 @@ static int ocelot_switch_init(struct ocelot_private *priv)
 	return 0;
 }
 
-static void ocelot_switch_flush(struct ocelot_private *priv)
-{
-	/* All Queues flush */
-	setbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
-	/* Allow to drain */
-	mdelay(1);
-	/* All Queues normal */
-	clrbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
-}
-
 static int ocelot_initialize(struct ocelot_private *priv)
 {
 	int ret, i;
@@ -463,7 +343,7 @@ static int ocelot_initialize(struct ocelot_private *priv)
 		writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
 
 	/* Flush queues */
-	ocelot_switch_flush(priv);
+	mscc_flush(priv->regs[QS], ocelot_regs_qs);
 
 	/* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
 	writel(SYS_FRM_AGING_ENA | (20000000 / 65),
@@ -479,62 +359,13 @@ static int ocelot_initialize(struct ocelot_private *priv)
 	return 0;
 }
 
-static inline int ocelot_vlant_wait_for_completion(struct ocelot_private *priv)
-{
-	unsigned int val, timeout = 10;
-
-	/* Wait for the issued mac table command to be completed, or timeout.
-	 * When the command read from ANA_TABLES_MACACCESS is
-	 * MACACCESS_CMD_IDLE, the issued command completed successfully.
-	 */
-	do {
-		val = readl(priv->regs[ANA] + ANA_TABLES_MACACCESS);
-		val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
-	} while (val != MACACCESS_CMD_IDLE && timeout--);
-
-	if (!timeout)
-		return -ETIMEDOUT;
-
-	return 0;
-}
-
-static int ocelot_mac_table_add(struct ocelot_private *priv,
-				const unsigned char mac[ETH_ALEN], int pgid)
-{
-	u32 macl = 0, mach = 0;
-	int ret;
-
-	/* Set the MAC address to handle and the vlan associated in a format
-	 * understood by the hardware.
-	 */
-	mach |= MAC_VID << 16;
-	mach |= ((u32)mac[0]) << 8;
-	mach |= ((u32)mac[1]) << 0;
-	macl |= ((u32)mac[2]) << 24;
-	macl |= ((u32)mac[3]) << 16;
-	macl |= ((u32)mac[4]) << 8;
-	macl |= ((u32)mac[5]) << 0;
-
-	writel(macl, priv->regs[ANA] + ANA_TABLES_MACLDATA);
-	writel(mach, priv->regs[ANA] + ANA_TABLES_MACHDATA);
-
-	writel(ANA_TABLES_MACACCESS_VALID |
-	       ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
-	       ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
-	       ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
-	       priv->regs[ANA] + ANA_TABLES_MACACCESS);
-
-	ret = ocelot_vlant_wait_for_completion(priv);
-
-	return ret;
-}
-
 static int ocelot_write_hwaddr(struct udevice *dev)
 {
 	struct ocelot_private *priv = dev_get_priv(dev);
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 
-	ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+	mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
+			   pdata->enetaddr, PGID_UNICAST);
 
 	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 
@@ -554,13 +385,15 @@ static int ocelot_start(struct udevice *dev)
 		return ret;
 
 	/* Set MAC address tables entries for CPU redirection */
-	ocelot_mac_table_add(priv, mac, PGID_BROADCAST);
+	mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
+			   PGID_BROADCAST);
 
 	writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
 	       priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
 
 	/* It should be setup latter in ocelot_write_hwaddr */
-	ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+	mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
+			   pdata->enetaddr, PGID_UNICAST);
 
 	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 
@@ -572,13 +405,8 @@ static int ocelot_send(struct udevice *dev, void *packet, int length)
 	struct ocelot_private *priv = dev_get_priv(dev);
 	u32 ifh[IFH_LEN];
 	int port = BIT(0);	/* use port 0 */
-	u8 grp = 0;		/* Send everything on CPU group 0 */
-	int i, count = (length + 3) / 4, last = length % 4;
 	u32 *buf = packet;
 
-	writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
-	       priv->regs[QS] + QS_INJ_CTRL(grp));
-
 	/*
 	 * Generate the IFH for frame injection
 	 *
@@ -595,91 +423,18 @@ static int ocelot_send(struct udevice *dev, void *packet, int length)
 	ifh[2] = (0xff & port) << 24;
 	ifh[3] = (IFH_TAG_TYPE_C << 16);
 
-	for (i = 0; i < IFH_LEN; i++)
-		writel(ifh[i], priv->regs[QS] + QS_INJ_WR(grp));
-
-	for (i = 0; i < count; i++)
-		writel(buf[i], priv->regs[QS] + QS_INJ_WR(grp));
-
-	/* Add padding */
-	while (i < (OCELOT_BUF_CELL_SZ / 4)) {
-		writel(0, priv->regs[QS] + QS_INJ_WR(grp));
-		i++;
-	}
-
-	/* Indicate EOF and valid bytes in last word */
-	writel(QS_INJ_CTRL_GAP_SIZE(1) |
-	       QS_INJ_CTRL_VLD_BYTES(length < OCELOT_BUF_CELL_SZ ? 0 : last) |
-	       QS_INJ_CTRL_EOF, priv->regs[QS] + QS_INJ_CTRL(grp));
-
-	/* Add dummy CRC */
-	writel(0, priv->regs[QS] + QS_INJ_WR(grp));
-
-	return 0;
+	return mscc_send(priv->regs[QS], ocelot_regs_qs,
+			 ifh, IFH_LEN, buf, length);
 }
 
 static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	struct ocelot_private *priv = dev_get_priv(dev);
-	u8 grp = 0;		/* Send everything on CPU group 0 */
 	u32 *rxbuf = (u32 *)net_rx_packets[0];
-	int i, byte_cnt = 0;
-	bool eof_flag = false, pruned_flag = false, abort_flag = false;
-
-	if (!(readl(priv->regs[QS] + QS_XTR_DATA_PRESENT) & BIT(grp)))
-		return -EAGAIN;
-
-	/* skip IFH */
-	for (i = 0; i < IFH_LEN; i++)
-		readl(priv->regs[QS] + QS_XTR_RD(grp));
-
-	while (!eof_flag) {
-		u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
-
-		switch (val) {
-		case XTR_NOT_READY:
-			debug("%d NOT_READY...?\n", byte_cnt);
-			break;
-		case XTR_ABORT:
-			/* really nedeed?? not done in linux */
-			*rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
-			abort_flag = true;
-			eof_flag = true;
-			debug("XTR_ABORT\n");
-			break;
-		case XTR_EOF_0:
-		case XTR_EOF_1:
-		case XTR_EOF_2:
-		case XTR_EOF_3:
-			byte_cnt += XTR_VALID_BYTES(val);
-			*rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
-			eof_flag = true;
-			debug("EOF\n");
-			break;
-		case XTR_PRUNED:
-			/* But get the last 4 bytes as well */
-			eof_flag = true;
-			pruned_flag = true;
-			debug("PRUNED\n");
-			/* fallthrough */
-		case XTR_ESCAPE:
-			*rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
-			byte_cnt += 4;
-			rxbuf++;
-			debug("ESCAPED\n");
-			break;
-		default:
-			*rxbuf = val;
-			byte_cnt += 4;
-			rxbuf++;
-		}
-	}
+	int byte_cnt;
 
-	if (abort_flag || pruned_flag || !eof_flag) {
-		debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
-		      abort_flag, pruned_flag, eof_flag);
-		return -EAGAIN;
-	}
+	byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
+			     false);
 
 	*packetp = net_rx_packets[0];
 

include/configs/gardena-smart-gateway-mt7688.h

@@ -7,7 +7,7 @@
 #define __CONFIG_GARDENA_SMART_GATEWAY_H
 
 /* CPU */
-#define CONFIG_SYS_MIPS_TIMER_FREQ	200000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ	290000000
 
 /* RAM */
 #define CONFIG_SYS_SDRAM_BASE		0x80000000

include/configs/linkit-smart-7688.h

@@ -7,7 +7,7 @@
 #define __CONFIG_LINKIT_SMART_7688_H
 
 /* CPU */
-#define CONFIG_SYS_MIPS_TIMER_FREQ	200000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ	290000000
 
 /* RAM */
 #define CONFIG_SYS_SDRAM_BASE		0x80000000