The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.

Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: NChenhui Zhao <b26998@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The current code use all the voltage range support by the host
controller to do the validation.  This will cause problem when
the host supports Low Voltage Range.  Change the validation
voltage to be based on board setup.
Signed-off-by: NLi Yang <leoli@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The max clock of MMC is 52MHz
Signed-off-by: NJerry Huang <Changm-Ming.Huang@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.

Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The current code use all the voltage range support by the host
controller to do the validation.  This will cause problem when
the host supports Low Voltage Range.  Change the validation
voltage to be based on board setup.
Signed-off-by: NLi Yang <leoli@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The max clock of MMC is 52MHz
Signed-off-by: NJerry Huang <Changm-Ming.Huang@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.

Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.
Signed-off-by: NP.V.Suresh <pala@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Commit 77c1458d caused the following compiler warnings:

fsl_esdhc.c: In function 'esdhc_pio_read_write':
fsl_esdhc.c:142: warning: assignment discards qualifiers from pointer target type
fsl_esdhc.c: In function 'esdhc_setup_data':
fsl_esdhc.c:169: warning: unused variable 'wml_value'
fsl_esdhc.c: In function 'esdhc_pio_read_write':
fsl_esdhc.c:164: warning: control reaches end of non-void function

Fix these.
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Dipen Dudhat <dipen.dudhat@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has been introduced to do data transfer using CPU.
Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com>

When we set the read or write watermark in WML we should maintain the
rest of the register as is, rather than using some hard coded value.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

To support multiple block read command we must set abort or use auto
CMD12.  If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We need to stop the clocks on 83xx/85xx as well as imx.  No need to make
this code conditional to just imx.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NStefano Babic <sbabic@denx.de>

The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.
Signed-off-by: NStefano Babic <sbabic@denx.de>

This patch implements fdt_fixup_esdhc() function that is used to fixup
the device tree.

The function adds status = "disabled" propery if esdhc pins muxed away,
otherwise it fixups clock-frequency for esdhc nodes.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

Now that response is a uint, we can drop all the casts.
Signed-off-by: NRabin Vincent <rabin@rab.in>

This uses the new MMC framework

Some contributions by Dave Liu <daveliu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>