Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling
ET1011C gigabit phy. which overrides get_link_speed function
from default implementation. This enables output of 125 MHz
reference clock on SYS_CLK pin.
Signed-off-by: NPrakash PM <prakash.pm@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Adds "DaVinci-EMAC" as the name of the device so that
it gets printed as "Using DaVinci-EMAC device"
during network access (dhcp, tftp) instead of empty name
in "Using" statement.This name also gets
reflected in 'ethact' env variable.
Signed-off-by: NHemant Pedanekar <hemantp@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Enabling the gigabit was overwriting the
previous configuration by setting up only GIGAFORCE and
GIG bits of MAC control register.
Modified to retain previous configuration while
gigabit enabling.
Signed-off-by: NPrakash PM <prakash.pm@ti.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Added support for MMC/SD cards for Davinci.  This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.
Signed-off-by: NAlagu Sankar <alagusankar@embwise.com>
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

Drop warnings due to unused variables.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.
Signed-off-by: NStefano Babic <sbabic@denx.de>

The MXC SPI driver didn't calculate the SPI clock up to
now and just used highest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.

The patch adds code to calculate and setup the SPI clock
frequency for transfers.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NStefano Babic <sbabic@denx.de>

We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
transmited.

The proper swapping in unaligned rx case is missing, so add it
as we need to put the received data into the rx buffer in the
correct byte order.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Tested-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

The patch adds helper funtions for basic access to the registers
of the MC9sdz60 chip (multifunctional device with RTC and CAN) via
I2C interface.
Signed-off-by: NStefano Babic <sbabic@denx.de>

There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and CAN/RTC chip).

The current driver uses the IIF bit in the status register
to check if the bus is busy or not. According to the manual,
this is not correct, because the IIB bit should be checked.
Not only, to check if a transfer is finished must be checked
the ICF bit, and this is not tested at all.

This patch comes from analyse with a corresponding driver
provided by Freescale as part of the LTIB tool. Comparing
the two drivers, it appears that the current u-boot driver checks
the wrong bits, and depending on race condition, the transfer
can be successful or not.

The patch gets rid also of own debug function (DPRINTF),
replaced with the general debug().

Tested on Freescale mx35pdk.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: NHeiko Schocher <hs@denx.de>

The patch adds UART support for the i.MX35 processor.
Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>
Acked-by: NScott Wood <scottwood@freescale.com>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Acked-by: NWolfgang Denk <wd@denx.de>

This patch add I2C interface for fsl_pmic driver support
Signed-off-by: NJason Liu <r64343@freescale.com>

This patch add I2C support for Freescale MX53 processor
Signed-off-by: NJason Liu <r64343@freescale.com>

This patch add mxc_gpio support for Freescale MX53 processor
Signed-off-by: NJason Liu <r64343@freescale.com>

This patch add UART support for Freescale MX53 processor
Signed-off-by: NJason Liu <r64343@freescale.com>

This patch add FEC support for Freescale MX53 processor
Signed-off-by: NJason Liu <r64343@freescale.com>

Make at91 header includes in soft_i2c depend only on CONFIG_AT91FAMILY
rather than individual SoCs.
Signed-off-by: NRyan Mallon <ryan@bluewatersys.com>
Acked-by: Reinhard Meyer<u-boot@emk-elektronik.de>

Faraday's ftpmu010 is a power managemnet unit which support cpu
sleep and frequency scaling. It has been integrated into many SoC.

This patch also move ftpmu010 to a proper place for later enhancement.
Signed-off-by: NMacpaul Lin <macpaul@andestech.com>

Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced the following
compiler warnings in the uec ethernet driver:

In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
                 from uec.c:32:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition
In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
                 from uec_phy.c:27:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition

Fix them be removing the duplication in the uec code and utlizing the
linux/mii.h version instead.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P1014 is similar to the P1010 processor with the following differences:

- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
	* TCP/IP acceleration and classification capabilities
	* IEEE 1588 support
	* Lossless flow control
	* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
  up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
  software watchdog timer, and four general-purpose timers
* Dual DUARTs
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This allows to change device and host MAC addresses without performing
reset.
Signed-off-by: NVitaly Kuzmichev <vkuzmichev@mvista.com>

Calling eth_bind at usb_eth_init time causes renaming of the network
device from 'usb_ether' to 'usb0'. Fixing this to keep the first name.
Signed-off-by: NVitaly Kuzmichev <vkuzmichev@mvista.com>

Since the ether may not be the only one usb gadget would be used
in the uboot, it is neccessary to do the register each time the
eth begin to work to make usb gadget driver less confussed when
we want to use two different usb gadget at the same time.

Usb gadget driver could simple ignore the register operation, if
it find the driver has been registered already.
Signed-off-by: NLei Wen <leiwen@marvell.com>

There's no compelling reason to have the output on bootup or the
"flinfo" command print "flash" in uppercase, so use the proper case
where appropriate.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

The lan91c96_detect_chip routine is not correct according
to the manual.
Signed-off-by: YanJun Yang <yangyj.ee@gmail.com>

Signed-off-by: NHeiko Schocher <hs@denx.de>

The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This change does the following:
- Adds printing of negotiated link width.  This information can be
  useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
  Previously boards that did not implement it would print unsightly
  output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
  clear that the "base address XYZ" value refers to the base address of
  the internal processor PCIe registers and not a standard PCI BAR
  value.
- Changes "PCIE" output to the standard "PCIe"

Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06

After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled.  After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that
may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new
generic code.

Based on patch by: Li Yang <leoli@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>