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  1. 07 4月, 2010 1 次提交
  3. 30 3月, 2010 1 次提交
  5. 06 1月, 2010 1 次提交
  7. 07 10月, 2009 1 次提交
    • S
      ppc4xx: Add PPC405EX(r) Rev D support · 56f14818
      由 Stefan Roese 提交于 
      Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>
      56f14818
  9. 25 9月, 2009 1 次提交
  11. 16 9月, 2009 1 次提交
  13. 08 9月, 2009 2 次提交
  15. 29 8月, 2009 3 次提交
  17. 30 7月, 2009 1 次提交
  19. 24 7月, 2009 1 次提交
  21. 30 6月, 2009 1 次提交
  23. 13 6月, 2009 2 次提交
  25. 31 3月, 2009 1 次提交
  27. 17 2月, 2009 3 次提交
    • P
      86xx: Update CPU info output on bootup · a1c8a719
      由 Peter Tyser 提交于 
      - Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
      a1c8a719
    • S
      mpc85xx: Add support for the P2020 · 8d949aff
      由 Srikanth Srinivasan 提交于 
      Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: NSrikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: NTravis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      8d949aff
    • K
      85xx: Fix how we map DDR memory · f8523cb0
      由 Kumar Gala 提交于 
      Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      f8523cb0
  29. 28 8月, 2008 1 次提交
  31. 18 7月, 2008 1 次提交
  33. 15 7月, 2008 2 次提交
  35. 11 7月, 2008 1 次提交
  37. 26 6月, 2008 1 次提交
  39. 20 6月, 2008 1 次提交
  41. 11 6月, 2008 1 次提交
    • K
      85xx: expose cpu identification · 4dbdb768
      由 Kumar Gala 提交于 
      The current cpu identification code is used just to return the name
of the processor at boot.  There are some other locations that the name
is useful (device tree setup).  Expose the functionality to other bits
of code.

Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out.  This is mainly to allow the most flexible use
of the name.  The device tree code tends to not care about the 'E' suffix.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      4dbdb768
  43. 04 6月, 2008 1 次提交
    • G
      ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling · c821b5f1
      由 Grant Erickson 提交于 
      This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
    Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>
      c821b5f1
  45. 14 5月, 2008 1 次提交
  47. 14 4月, 2008 2 次提交
  49. 27 3月, 2008 1 次提交
    • A
      Update SVR numbers to expand support · 1ced1216
      由 Andy Fleming 提交于 
      FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      1ced1216
  51. 15 3月, 2008 1 次提交
  53. 10 1月, 2008 1 次提交
  55. 01 11月, 2007 2 次提交
  57. 18 10月, 2007 1 次提交
  59. 14 8月, 2007 1 次提交
    • A
      85xx start.S cleanup and exception support · 61a21e98
      由 Andy Fleming 提交于 
      From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>
      61a21e98
  61. 11 8月, 2007 1 次提交