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体验新版 GitCode,发现更多精彩内容 >>
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dbbd1257
编写于
10月 05, 2007
作者:
S
Stefan Roese
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
ppc4xx: Add PPC405EX support
Signed-off-by:
N
Stefan Roese
<
sr@denx.de
>
上级
1d7b874e
变更
21
展开全部
隐藏空白更改
内联
并排
Showing
21 changed file
with
1205 addition
and
145 deletion
+1205
-145
common/serial.c
common/serial.c
+4
-2
cpu/ppc4xx/4xx_enet.c
cpu/ppc4xx/4xx_enet.c
+89
-24
cpu/ppc4xx/Makefile
cpu/ppc4xx/Makefile
+1
-1
cpu/ppc4xx/cpu.c
cpu/ppc4xx/cpu.c
+46
-17
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/cpu_init.c
+11
-3
cpu/ppc4xx/interrupts.c
cpu/ppc4xx/interrupts.c
+10
-10
cpu/ppc4xx/miiphy.c
cpu/ppc4xx/miiphy.c
+18
-4
cpu/ppc4xx/ndfc.c
cpu/ppc4xx/ndfc.c
+2
-1
cpu/ppc4xx/serial.c
cpu/ppc4xx/serial.c
+38
-4
cpu/ppc4xx/speed.c
cpu/ppc4xx/speed.c
+174
-6
cpu/ppc4xx/start.S
cpu/ppc4xx/start.S
+39
-30
cpu/ppc4xx/vecnum.h
cpu/ppc4xx/vecnum.h
+104
-0
include/405_mal.h
include/405_mal.h
+3
-1
include/4xx_i2c.h
include/4xx_i2c.h
+1
-1
include/asm-ppc/processor.h
include/asm-ppc/processor.h
+4
-0
include/asm-ppc/u-boot.h
include/asm-ppc/u-boot.h
+1
-0
include/common.h
include/common.h
+2
-2
include/ppc405.h
include/ppc405.h
+644
-31
include/ppc440.h
include/ppc440.h
+1
-1
include/ppc4xx_enet.h
include/ppc4xx_enet.h
+10
-5
include/serial.h
include/serial.h
+3
-2
未找到文件。
common/serial.c
浏览文件 @
dbbd1257
...
...
@@ -41,7 +41,8 @@ struct serial_device *default_serial_console (void)
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return
&
serial_scc_device
;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|| defined(CONFIG_MPC5xxx)
#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return
&
eserial1_device
;
...
...
@@ -91,7 +92,8 @@ void serial_initialize (void)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|| defined(CONFIG_MPC5xxx)
serial_register
(
&
serial0_device
);
serial_register
(
&
serial1_device
);
#endif
...
...
cpu/ppc4xx/4xx_enet.c
浏览文件 @
dbbd1257
...
...
@@ -133,13 +133,15 @@
#define BI_PHYMODE_GMII 3
#define BI_PHYMODE_RTBI 4
#define BI_PHYMODE_TBI 5
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define BI_PHYMODE_SMII 6
#define BI_PHYMODE_MII 7
#endif
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
...
...
@@ -172,6 +174,12 @@ struct eth_device *emac0_dev = NULL;
#define CONFIG_EMAC_NR_START 0
#endif
#if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
#else
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
#endif
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
...
...
@@ -197,7 +205,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
{
EMAC_4XX_HW_PST
hw_p
=
dev
->
priv
;
uint32_t
failsafe
=
10000
;
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
unsigned
long
mfr
;
#endif
...
...
@@ -221,7 +231,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
}
/* EMAC RESET */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* provide clocks for EMAC internal loopback */
mfsdr
(
sdr_mfr
,
mfr
);
mfr
|=
SDR0_MFR_ETH_CLK_SEL_V
(
hw_p
->
devnum
);
...
...
@@ -230,7 +242,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
out32
(
EMAC_M0
+
hw_p
->
hw_addr
,
EMAC_M0_SRST
);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* remove clocks for EMAC internal loopback */
mfsdr
(
sdr_mfr
,
mfr
);
mfr
&=
~
SDR0_MFR_ETH_CLK_SEL_V
(
hw_p
->
devnum
);
...
...
@@ -389,6 +403,38 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
}
#endif
/* CONFIG_440EPX */
#if defined(CONFIG_405EX)
int
ppc_4xx_eth_setup_bridge
(
int
devnum
,
bd_t
*
bis
)
{
u32
gmiifer
=
0
;
/*
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2007-09-19
*/
switch
(
1
)
{
case
1
:
/* 2 x RGMII ports */
out32
(
RGMII_FER
,
0x00000055
);
bis
->
bi_phymode
[
0
]
=
BI_PHYMODE_RGMII
;
bis
->
bi_phymode
[
1
]
=
BI_PHYMODE_RGMII
;
break
;
case
2
:
/* 2 x SMII ports */
break
;
default:
break
;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
gmiifer
=
in32
(
RGMII_FER
);
gmiifer
|=
(
1
<<
(
19
-
devnum
));
out32
(
RGMII_FER
,
gmiifer
);
return
((
int
)
0x0
);
}
#endif
/* CONFIG_405EX */
static
int
ppc_4xx_eth_init
(
struct
eth_device
*
dev
,
bd_t
*
bis
)
{
int
i
,
j
;
...
...
@@ -402,19 +448,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
unsigned
short
reg_short
;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
sys_info_t
sysinfo
;
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
int
ethgroup
=
-
1
;
#endif
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
unsigned
long
mfr
;
#endif
EMAC_4XX_HW_PST
hw_p
=
dev
->
priv
;
/* before doing anything, figure out if we have a MAC address */
...
...
@@ -426,7 +474,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info
(
&
sysinfo
);
#endif
...
...
@@ -498,12 +547,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32
(
ZMII_SSR
,
ZMII_SSR_SP
<<
ZMII_SSR_V
(
devnum
));
#endif
/* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_405EX)
ethgroup
=
ppc_4xx_eth_setup_bridge
(
devnum
,
bis
);
#endif
__asm__
volatile
(
"eieio"
);
/* reset emac so we have access to the phy */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* provide clocks for EMAC internal loopback */
mfsdr
(
sdr_mfr
,
mfr
);
mfr
|=
SDR0_MFR_ETH_CLK_SEL_V
(
devnum
);
...
...
@@ -521,8 +574,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if
(
failsafe
<=
0
)
printf
(
"
\n
Problem resetting EMAC!
\n
"
);
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* remove clocks for EMAC internal loopback */
mfsdr
(
sdr_mfr
,
mfr
);
mfr
&=
~
SDR0_MFR_ETH_CLK_SEL_V
(
devnum
);
...
...
@@ -531,7 +585,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
/* Whack the M1 register */
mode_reg
=
0x0
;
mode_reg
&=
~
0x00000038
;
...
...
@@ -591,7 +646,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
#if defined(CONFIG_CIS8201_PHY)
/*
...
...
@@ -723,7 +779,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
}
#endif
/* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
if
(
speed
==
1000
)
reg
=
(
RGMII_SSR_SP_1000MBPS
<<
RGMII_SSR_V
(
devnum
));
else
if
(
speed
==
100
)
...
...
@@ -740,7 +797,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
mtdcr
(
malmcr
,
MAL_CR_PLBB
|
MAL_CR_OPBBL
|
MAL_CR_LEA
|
MAL_CR_PLBLT_DEFAULT
|
MAL_CR_EOPIE
|
0x00330000
);
#else
...
...
@@ -978,8 +1036,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/*
* Connect interrupt service routines
*/
irq_install_handler
(
VECNUM_ETH0
+
(
hw_p
->
devnum
*
2
),
(
interrupt_handler_t
*
)
enetInt
,
dev
);
irq_install_handler
(
ETH_IRQ_NUM
(
hw_p
->
devnum
),
(
interrupt_handler_t
*
)
enetInt
,
dev
);
}
mtmsr
(
msr
);
/* enable interrupts again */
...
...
@@ -1059,7 +1117,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
}
#if defined (CONFIG_440)
#if defined (CONFIG_440)
|| defined(CONFIG_405EX)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*
...
...
@@ -1073,7 +1131,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
#define UIC0SR uic0sr
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UICMSR_ETHX uic0msr
#define UICSR_ETHX uic0sr
#else
...
...
@@ -1601,7 +1660,11 @@ int ppc_4xx_eth_initialize (bd_t * bis)
bis
->
bi_phynum
[
3
]
=
CONFIG_PHY3_ADDR
;
bis
->
bi_phymode
[
2
]
=
2
;
bis
->
bi_phymode
[
3
]
=
2
;
#endif
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
ppc_4xx_eth_setup_bridge
(
0
,
bis
);
#endif
...
...
@@ -1649,7 +1712,9 @@ int ppc_4xx_eth_initialize (bd_t * bis)
if
(
0
==
virgin
)
{
/* set the MAL IER ??? names may change with new spec ??? */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
mal_ier
=
MAL_IER_PT
|
MAL_IER_PRE
|
MAL_IER_PWE
|
MAL_IER_DE
|
MAL_IER_OTE
|
MAL_IER_OE
|
MAL_IER_PE
;
...
...
cpu/ppc4xx/Makefile
浏览文件 @
dbbd1257
...
...
@@ -30,7 +30,7 @@ SOBJS = dcr.o
COBJS
=
40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o
\
4xx_pci.o 4xx_pcie.o 4xx_enet.o
\
bedbug_405.o commproc.o
\
cpu.o cpu_init.o gpio.o i2c.o interrupts.o
\
cpu.o cpu_init.o
fdt.o
gpio.o i2c.o interrupts.o
\
miiphy.o ndfc.o sdram.o serial.o speed.o
\
tlb.o traps.o usb_ohci.o usb.o usbdev.o
...
...
cpu/ppc4xx/cpu.c
浏览文件 @
dbbd1257
/*
* (C) Copyright 2000-200
6
* (C) Copyright 2000-200
7
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -45,15 +45,6 @@ DECLARE_GLOBAL_DATA_PTR;
void
board_reset
(
void
);
#endif
#if defined(CONFIG_440)
#define FREQ_EBC (sys_info.freqEPB)
#elif defined(CONFIG_405EZ)
#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
sys_info.pllExtBusDiv)
#else
#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
#if defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
...
...
@@ -76,7 +67,8 @@ int pci_async_enabled(void)
}
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
int
pci_arbiter_enabled
(
void
)
{
#if defined(CONFIG_405GP)
...
...
@@ -110,7 +102,8 @@ int pci_arbiter_enabled(void)
#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
#define I2C_BOOTROM
...
...
@@ -207,6 +200,21 @@ static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
'I'
,
'x'
,
'K'
,
'L'
,
'M'
,
'N'
,
'O'
,
'P'
};
#endif
#if defined(CONFIG_405EX)
#define SDR0_PINSTP_SHIFT 29
static
char
*
bootstrap_str
[]
=
{
"EBC (8 bits)"
,
"EBC (16 bits)"
,
"EBC (16 bits)"
,
"NAND (8 bits)"
,
"NAND (8 bits)"
,
"I2C (Addr 0x54)"
,
"EBC (8 bits)"
,
"I2C (Addr 0x52)"
,
};
static
char
bootstrap_char
[]
=
{
'A'
,
'B'
,
'C'
,
'D'
,
'E'
,
'G'
,
'F'
,
'H'
};
#endif
#if defined(SDR0_PINSTP_SHIFT)
static
int
bootstrap_option
(
void
)
{
...
...
@@ -241,7 +249,8 @@ int checkcpu (void)
puts
(
"AMCC PowerPC 4"
);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ)
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX)
puts
(
"05"
);
#endif
#if defined(CONFIG_440)
...
...
@@ -293,6 +302,26 @@ int checkcpu (void)
puts
(
"EZ Rev. A"
);
break
;
case
PVR_405EX1_RA
:
puts
(
"EX Rev. A"
);
strcpy
(
addstr
,
"Security support"
);
break
;
case
PVR_405EX2_RA
:
puts
(
"EX Rev. A"
);
strcpy
(
addstr
,
"No Security support"
);
break
;
case
PVR_405EXR1_RA
:
puts
(
"EXr Rev. A"
);
strcpy
(
addstr
,
"Security support"
);
break
;
case
PVR_405EXR2_RA
:
puts
(
"EXr Rev. A"
);
strcpy
(
addstr
,
"No Security support"
);
break
;
#if defined(CONFIG_440)
case
PVR_440GP_RB
:
puts
(
"GP Rev. B"
);
...
...
@@ -424,7 +453,7 @@ int checkcpu (void)
printf
(
" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)
\n
"
,
strmhz
(
buf
,
clock
),
sys_info
.
freqPLB
/
1000000
,
get_OPB_freq
()
/
1000000
,
FREQ_
EBC
/
1000000
);
sys_info
.
freq
EBC
/
1000000
);
if
(
addstr
[
0
]
!=
0
)
printf
(
" %s
\n
"
,
addstr
);
...
...
@@ -437,7 +466,7 @@ int checkcpu (void)
printf
(
"Boot ROM Location %s
\n
"
,
bootstrap_str
[
bootstrap_option
()]);
#endif
/* SDR0_PINSTP_SHIFT */
#if defined(CONFIG_PCI)
#if defined(CONFIG_PCI)
&& !defined(CONFIG_405EX)
printf
(
" Internal PCI arbiter %sabled"
,
pci_arbiter_enabled
()
?
"en"
:
"dis"
);
#endif
...
...
@@ -450,11 +479,11 @@ int checkcpu (void)
}
#endif
#if defined(CONFIG_PCI)
#if defined(CONFIG_PCI)
&& !defined(CONFIG_405EX)
putc
(
'\n'
);
#endif
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
|| defined(CONFIG_405EX)
printf
(
" 16 kB I-Cache 16 kB D-Cache"
);
#elif defined(CONFIG_440)
printf
(
" 32 kB I-Cache 32 kB D-Cache"
);
...
...
cpu/ppc4xx/cpu_init.c
浏览文件 @
dbbd1257
/*
* (C) Copyright 2000-200
6
* (C) Copyright 2000-200
7
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -112,7 +112,7 @@ cpu_init_f (void)
unsigned
long
val
;
#endif
#if defined(CONFIG_405EP)
#if defined(CONFIG_405EP)
|| defined (CONFIG_405EX)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
...
...
@@ -128,13 +128,21 @@ cpu_init_f (void)
out32
(
GPIO0_ISR1L
,
CFG_GPIO0_ISR1L
);
out32
(
GPIO0_TSRH
,
CFG_GPIO0_TSRH
);
/* three-state select */
out32
(
GPIO0_TSRL
,
CFG_GPIO0_TSRL
);
#if defined(CFG_GPIO0_ISR2H)
out32
(
GPIO0_ISR2H
,
CFG_GPIO0_ISR2H
);
out32
(
GPIO0_ISR2L
,
CFG_GPIO0_ISR2L
);
#endif
#if defined (CFG_GPIO0_TCR)
out32
(
GPIO0_TCR
,
CFG_GPIO0_TCR
);
/* enable output driver for outputs */
#endif
#if defined (CONFIG_450EP)
/*
* Set EMAC noise filter bits
*/
mtdcr
(
cpc0_epctl
,
CPC0_EPRCSR_E0NFE
|
CPC0_EPRCSR_E1NFE
);
#endif
/* CONFIG_405EP */
#endif
/* CONFIG_405EP */
#if defined(CFG_440_GPIO_TABLE)
gpio_set_chip_configuration
();
...
...
@@ -146,7 +154,7 @@ cpu_init_f (void)
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405))
defined(CONFIG_405
EX) || defined(CONFIG_405
))
/*
* Move the next instructions into icache, since these modify the flash
* we are running from!
...
...
cpu/ppc4xx/interrupts.c
浏览文件 @
dbbd1257
...
...
@@ -52,7 +52,7 @@ struct irq_action {
static
struct
irq_action
irq_vecs
[
32
];
void
uic0_interrupt
(
void
*
parms
);
/* UIC0 handler */
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
static
struct
irq_action
irq_vecs1
[
32
];
/* For UIC1 */
void
uic1_interrupt
(
void
*
parms
);
/* UIC1 handler */
...
...
@@ -116,7 +116,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
irq_vecs
[
vec
].
handler
=
NULL
;
irq_vecs
[
vec
].
arg
=
NULL
;
irq_vecs
[
vec
].
count
=
0
;
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
irq_vecs1
[
vec
].
handler
=
NULL
;
irq_vecs1
[
vec
].
arg
=
NULL
;
irq_vecs1
[
vec
].
count
=
0
;
...
...
@@ -172,7 +172,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
set_evpr
(
0x00000000
);
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler
(
VECNUM_UIC1NC
,
uic1_interrupt
,
0
);
...
...
@@ -378,7 +378,7 @@ void uic0_interrupt( void * parms)
#endif
/* CONFIG_440GX */
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
/* Handler for UIC1 interrupt */
void
uic1_interrupt
(
void
*
parms
)
{
...
...
@@ -525,7 +525,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
struct
irq_action
*
irqa
=
irq_vecs
;
int
i
=
vec
;
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if
((
vec
>
31
)
&&
(
vec
<
64
))
{
...
...
@@ -553,7 +553,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
irqa
[
i
].
handler
=
handler
;
irqa
[
i
].
arg
=
arg
;
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if
((
vec
>
31
)
&&
(
vec
<
64
))
...
...
@@ -577,7 +577,7 @@ void irq_free_handler (int vec)
struct
irq_action
*
irqa
=
irq_vecs
;
int
i
=
vec
;
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if
((
vec
>
31
)
&&
(
vec
<
64
))
{
...
...
@@ -599,7 +599,7 @@ void irq_free_handler (int vec)
vec, irq_vecs[vec].handler);
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if
((
vec
>
31
)
&&
(
vec
<
64
))
...
...
@@ -641,7 +641,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int
vec
;
printf
(
"
\n
Interrupt-Information:
\n
"
);
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
printf
(
"
\n
UIC 0
\n
"
);
#endif
printf
(
"Nr Routine Arg Count
\n
"
);
...
...
@@ -656,7 +656,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
}
#if defined(CONFIG_440)
#if defined(CONFIG_440)
|| defined(CONFIG_405EX)
printf
(
"
\n
UIC 1
\n
"
);
printf
(
"Nr Routine Arg Count
\n
"
);
...
...
cpu/ppc4xx/miiphy.c
浏览文件 @
dbbd1257
...
...
@@ -141,6 +141,16 @@ unsigned int miiphy_getemac_offset (void)
return
(
eoffset
);
#else
#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
unsigned
long
rgmii
;
int
devnum
=
1
;
rgmii
=
in32
(
RGMII_FER
);
if
(
rgmii
&
(
1
<<
(
19
-
devnum
)))
return
0x100
;
#endif
return
0
;
#endif
}
...
...
@@ -174,7 +184,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
sta_reg
=
reg
;
/* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#if defined(CONFIG_IBM_EMAC4_V4)
/* EMAC4 V4 changed bit setting */
sta_reg
=
(
sta_reg
&
~
EMAC_STACR_OP_MASK
)
|
EMAC_STACR_READ
;
#else
...
...
@@ -186,7 +197,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
!defined(CONFIG_405EX)
sta_reg
=
sta_reg
|
CONFIG_PHY_CLK_FREQ
;
#endif
sta_reg
=
sta_reg
|
(
addr
<<
5
);
/* Phy address */
...
...
@@ -248,7 +260,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
sta_reg
=
reg
;
/* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#if defined(CONFIG_IBM_EMAC4_V4)
/* EMAC4 V4 changed bit setting */
sta_reg
=
(
sta_reg
&
~
EMAC_STACR_OP_MASK
)
|
EMAC_STACR_WRITE
;
#else
...
...
@@ -260,7 +273,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
!defined(CONFIG_405EX)
sta_reg
=
sta_reg
|
CONFIG_PHY_CLK_FREQ
;
/* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg
=
sta_reg
|
((
unsigned
long
)
addr
<<
5
);
/* Phy address */
...
...
cpu/ppc4xx/ndfc.c
浏览文件 @
dbbd1257
...
...
@@ -34,7 +34,7 @@
#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EZ))
defined(CONFIG_405EZ)
|| defined(CONFIG_405EX)
)
#include <nand.h>
#include <linux/mtd/ndfc.h>
...
...
@@ -222,6 +222,7 @@ int board_nand_init(struct nand_chip *nand)
*/
board_nand_select_device
(
nand
,
cs
);
out_be32
((
u32
*
)(
base
+
NDFC_BCFG0
+
(
cs
<<
2
)),
0x80002222
);
return
0
;
}
...
...
cpu/ppc4xx/serial.c
浏览文件 @
dbbd1257
...
...
@@ -266,7 +266,7 @@ int serial_tstc ()
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440)
defined(CONFIG_4
05EX) || defined(CONFIG_4
40)
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
...
...
@@ -318,6 +318,15 @@ int serial_tstc ()
#define UCR0_UDIV_POS 0
#define UCR1_UDIV_POS 8
#define UDIV_MAX 127
#elif defined(CONFIG_405EX)
#define UART0_BASE 0xef600200
#define UART1_BASE 0xef600300
#define CR0_MASK 0x000000ff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#else
/* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
...
...
@@ -391,7 +400,8 @@ typedef struct {
volatile
static
serial_buffer_t
buf_info
;
#endif
#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
!defined(CFG_EXT_SERIAL_CLOCK)
static
void
serial_divs
(
int
baudrate
,
unsigned
long
*
pudiv
,
unsigned
short
*
pbdiv
)
{
...
...
@@ -572,7 +582,31 @@ int serial_init (void)
unsigned
short
bdiv
;
volatile
char
val
;
#if defined(CONFIG_405EZ)
#ifdef CONFIG_405EX
clk
=
tmp
=
0
;
mfsdr
(
UART0_SDR
,
reg
);
reg
&=
~
CR0_MASK
;
#ifdef CFG_EXT_SERIAL_CLOCK
reg
|=
CR0_EXTCLK_ENA
;
udiv
=
1
;
tmp
=
gd
->
baudrate
*
16
;
bdiv
=
(
CFG_EXT_SERIAL_CLOCK
+
tmp
/
2
)
/
tmp
;
#else
serial_divs
(
gd
->
baudrate
,
&
udiv
,
&
bdiv
);
#endif
reg
|=
(
udiv
-
UDIV_SUBTRACT
)
<<
CR0_UDIV_POS
;
/* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
mtsdr
(
UART0_SDR
,
reg
);
#if defined(UART1_SDR)
mtsdr
(
UART1_SDR
,
reg
);
#endif
#elif defined(CONFIG_405EZ)
serial_divs
(
gd
->
baudrate
,
&
udiv
,
&
bdiv
);
clk
=
tmp
=
reg
=
0
;
#else
...
...
@@ -608,7 +642,7 @@ int serial_init (void)
#endif
/* CONFIG_405EP */
tmp
=
gd
->
baudrate
*
udiv
*
16
;
bdiv
=
(
clk
+
tmp
/
2
)
/
tmp
;
#endif
/* CONFIG_405E
Z
*/
#endif
/* CONFIG_405E
X
*/
out8
(
UART_BASE
+
UART_LCR
,
0x80
);
/* set DLAB bit */
out8
(
UART_BASE
+
UART_DLL
,
bdiv
);
/* set baudrate divisor */
...
...
cpu/ppc4xx/speed.c
浏览文件 @
dbbd1257
/*
* (C) Copyright 2000
* (C) Copyright 2000
-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -263,7 +263,7 @@ void get_sys_info (sys_info_t *sysInfo)
sysInfo
->
freqProcessor
=
sysInfo
->
freqVCOMhz
/
sysInfo
->
pllFwdDivA
;
sysInfo
->
freqPLB
=
sysInfo
->
freqVCOMhz
/
sysInfo
->
pllFwdDivB
/
prbdv0
;
sysInfo
->
freqOPB
=
sysInfo
->
freqPLB
/
sysInfo
->
pllOpbDiv
;
sysInfo
->
freqE
PB
=
sysInfo
->
freqPLB
/
sysInfo
->
pllExtBusDiv
;
sysInfo
->
freqE
BC
=
sysInfo
->
freqPLB
/
sysInfo
->
pllExtBusDiv
;
sysInfo
->
freqPCI
=
sysInfo
->
freqPLB
/
sysInfo
->
pllPciDiv
;
/* Figure which timer source to use */
...
...
@@ -317,7 +317,7 @@ void get_sys_info (sys_info_t * sysInfo)
if
(
get_pvr
()
==
PVR_440GP_RB
)
/* Rev B divs an extra 2 -- geez! */
sysInfo
->
freqPLB
>>=
1
;
sysInfo
->
freqOPB
=
sysInfo
->
freqPLB
/
sysInfo
->
pllOpbDiv
;
sysInfo
->
freqE
PB
=
sysInfo
->
freqOPB
/
sysInfo
->
pllExtBusDiv
;
sysInfo
->
freqE
BC
=
sysInfo
->
freqOPB
/
sysInfo
->
pllExtBusDiv
;
}
#else
...
...
@@ -393,7 +393,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo
->
freqProcessor
=
sysInfo
->
freqVCOMhz
/
sysInfo
->
pllFwdDivA
;
sysInfo
->
freqPLB
=
sysInfo
->
freqVCOMhz
/
sysInfo
->
pllFwdDivB
/
prbdv0
;
sysInfo
->
freqOPB
=
sysInfo
->
freqPLB
/
sysInfo
->
pllOpbDiv
;
sysInfo
->
freqE
PB
=
sysInfo
->
freqOPB
/
sysInfo
->
pllExtBusDiv
;
sysInfo
->
freqE
BC
=
sysInfo
->
freqOPB
/
sysInfo
->
pllExtBusDiv
;
#if defined(CONFIG_YUCCA)
/* Determine PCI Clock Period */
...
...
@@ -733,6 +733,8 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
* Determine PLB clock frequency
*/
sysInfo
->
freqPLB
=
sysInfo
->
freqProcessor
/
sysInfo
->
pllPlbDiv
;
sysInfo
->
freqEBC
=
sysInfo
->
freqPLB
/
sysInfo
->
pllExtBusDiv
;
}
...
...
@@ -856,6 +858,9 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
*/
sysInfo
->
freqPLB
=
(
CONFIG_SYS_CLK_FREQ
*
m
)
/
sysInfo
->
pllFwdDiv
/
sysInfo
->
pllPlbDiv
;
sysInfo
->
freqEBC
=
(
CONFIG_SYS_CLK_FREQ
*
sysInfo
->
pllFbkDiv
)
/
sysInfo
->
pllExtBusDiv
;
}
/********************************************
...
...
@@ -874,13 +879,175 @@ ulong get_OPB_freq (void)
return
val
;
}
#elif defined(CONFIG_405EX)
/*
* TODO: We need to get the CPR registers and calculate these values correctly!!!!
* We need the specs!!!!
*/
static
unsigned
char
get_fbdv
(
unsigned
char
index
)
{
unsigned
char
ret
=
0
;
/* This is table should be 256 bytes.
* Only take first 52 values.
*/
unsigned
char
fbdv_tb
[]
=
{
0x00
,
0xff
,
0x7f
,
0xfd
,
0x7a
,
0xf5
,
0x6a
,
0xd5
,
0x2a
,
0xd4
,
0x29
,
0xd3
,
0x26
,
0xcc
,
0x19
,
0xb3
,
0x67
,
0xce
,
0x1d
,
0xbb
,
0x77
,
0xee
,
0x5d
,
0xba
,
0x74
,
0xe9
,
0x52
,
0xa5
,
0x4b
,
0x96
,
0x2c
,
0xd8
,
0x31
,
0xe3
,
0x46
,
0x8d
,
0x1b
,
0xb7
,
0x6f
,
0xde
,
0x3d
,
0xfb
,
0x76
,
0xed
,
0x5a
,
0xb5
,
0x6b
,
0xd6
,
0x2d
,
0xdb
,
0x36
,
0xec
,
};
if
((
index
&
0x7f
)
==
0
)
return
1
;
while
(
ret
<
sizeof
(
fbdv_tb
))
{
if
(
fbdv_tb
[
ret
]
==
index
)
break
;
ret
++
;
}
ret
++
;
return
ret
;
}
#define PLL_FBK_PLL_LOCAL 0
#define PLL_FBK_CPU 1
#define PLL_FBK_PERCLK 5
void
get_sys_info
(
sys_info_t
*
sysInfo
)
{
unsigned
long
sysClkPeriodPs
=
ONE_BILLION
/
(
CONFIG_SYS_CLK_FREQ
/
1000
);
unsigned
long
m
=
1
;
unsigned
int
tmp
;
unsigned
char
fwdva
[
16
]
=
{
1
,
2
,
14
,
9
,
4
,
11
,
16
,
13
,
12
,
5
,
6
,
15
,
10
,
7
,
8
,
3
,
};
unsigned
char
sel
,
cpudv0
,
plb2xDiv
;
mfcpr
(
cpr0_plld
,
tmp
);
/*
* Determine forward divider A
*/
sysInfo
->
pllFwdDiv
=
fwdva
[((
tmp
>>
16
)
&
0x0f
)];
/* FWDVA */
/*
* Determine FBK_DIV.
*/
sysInfo
->
pllFbkDiv
=
get_fbdv
(((
tmp
>>
24
)
&
0x0ff
));
/* FBDV */
/*
* Determine PLBDV0
*/
sysInfo
->
pllPlbDiv
=
2
;
/*
* Determine PERDV0
*/
mfcpr
(
cpr0_perd
,
tmp
);
tmp
=
(
tmp
>>
24
)
&
0x03
;
sysInfo
->
pllExtBusDiv
=
(
tmp
==
0
)
?
4
:
tmp
;
/*
* Determine OPBDV0
*/
mfcpr
(
cpr0_opbd
,
tmp
);
tmp
=
(
tmp
>>
24
)
&
0x03
;
sysInfo
->
pllOpbDiv
=
(
tmp
==
0
)
?
4
:
tmp
;
/* Determine PLB2XDV0 */
mfcpr
(
cpr0_plbd
,
tmp
);
tmp
=
(
tmp
>>
16
)
&
0x07
;
plb2xDiv
=
(
tmp
==
0
)
?
8
:
tmp
;
/* Determine CPUDV0 */
mfcpr
(
cpr0_cpud
,
tmp
);
tmp
=
(
tmp
>>
24
)
&
0x07
;
cpudv0
=
(
tmp
==
0
)
?
8
:
tmp
;
/* Determine SEL(5:7) in CPR0_PLLC */
mfcpr
(
cpr0_pllc
,
tmp
);
sel
=
(
tmp
>>
24
)
&
0x07
;
/*
* Determine the M factor
* PLL local: M = FBDV
* CPU clock: M = FBDV * FWDVA * CPUDV0
* PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0
*
*/
switch
(
sel
)
{
case
PLL_FBK_CPU
:
m
=
sysInfo
->
pllFwdDiv
*
cpudv0
;
break
;
case
PLL_FBK_PERCLK
:
m
=
sysInfo
->
pllFwdDiv
*
plb2xDiv
*
2
*
sysInfo
->
pllOpbDiv
*
sysInfo
->
pllExtBusDiv
;
break
;
case
PLL_FBK_PLL_LOCAL
:
break
;
default:
printf
(
"%s unknown m
\n
"
,
__FUNCTION__
);
return
;
}
m
*=
sysInfo
->
pllFbkDiv
;
/*
* Determine VCO clock frequency
*/
sysInfo
->
freqVCOHz
=
(
1000000000000LL
*
(
unsigned
long
long
)
m
)
/
(
unsigned
long
long
)
sysClkPeriodPs
;
/*
* Determine CPU clock frequency
*/
sysInfo
->
freqProcessor
=
sysInfo
->
freqVCOHz
/
(
sysInfo
->
pllFwdDiv
*
cpudv0
);
/*
* Determine PLB clock frequency, ddr1x should be the same
*/
sysInfo
->
freqPLB
=
sysInfo
->
freqVCOHz
/
(
sysInfo
->
pllFwdDiv
*
plb2xDiv
*
2
);
sysInfo
->
freqOPB
=
sysInfo
->
freqPLB
/
sysInfo
->
pllOpbDiv
;
sysInfo
->
freqDDR
=
sysInfo
->
freqPLB
;
sysInfo
->
freqEBC
=
sysInfo
->
freqOPB
/
sysInfo
->
pllExtBusDiv
;
}
/********************************************
* get_OPB_freq
* return OPB bus freq in Hz
*********************************************/
ulong
get_OPB_freq
(
void
)
{
ulong
val
=
0
;
PPC405_SYS_INFO
sys_info
;
get_sys_info
(
&
sys_info
);
val
=
sys_info
.
freqPLB
/
sys_info
.
pllOpbDiv
;
return
val
;
}
#endif
int
get_clocks
(
void
)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440) || defined(CONFIG_405)
defined(CONFIG_405EX) || defined(CONFIG_405) || \
defined(CONFIG_440)
sys_info_t
sys_info
;
get_sys_info
(
&
sys_info
);
...
...
@@ -907,7 +1074,8 @@ ulong get_bus_freq (ulong dummy)
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440) || defined(CONFIG_405)
defined(CONFIG_405EX) || defined(CONFIG_405) || \
defined(CONFIG_440)
sys_info_t
sys_info
;
get_sys_info
(
&
sys_info
);
...
...
cpu/ppc4xx/start.S
浏览文件 @
dbbd1257
...
...
@@ -800,7 +800,7 @@ _start:
/*-----------------------------------------------------------------------
*/
/
*
Enable
two
128
MB
cachable
regions
.
*/
/*-----------------------------------------------------------------------
*/
addis
r1
,
r0
,
0x
8
000
addis
r1
,
r0
,
0x
c
000
addi
r1
,
r1
,
0x0001
mticcr
r1
/*
instruction
cache
*/
...
...
@@ -823,12 +823,23 @@ _start:
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined
(
CONFIG_405EP
)
|
| defined(CONFIG_405EZ) |
|
\
defined
(
CONFIG_405
)
defined
(
CONFIG_405
EX
)
||
defined
(
CONFIG_405
)
/*-----------------------------------------------------------------------
*/
/
*
Clear
and
set
up
some
registers
.
*/
/*-----------------------------------------------------------------------
*/
addi
r4
,
r0
,
0x0000
#if !defined(CONFIG_405EX)
mtspr
sgr
,
r4
#else
/
*
*
On
40
5
EX
,
completely
clearing
the
SGR
leads
to
PPC
hangup
*
upon
PCIe
configuration
access
.
The
PCIe
memory
regions
*
need
to
be
guarded
!
*/
lis
r3
,
0x0000
ori
r3
,
r3
,
0x7FFC
mtspr
sgr
,
r3
#endif
mtspr
dcwr
,
r4
mtesr
r4
/*
clear
Exception
Syndrome
Reg
*/
mttcr
r4
/*
clear
Timer
Control
Reg
*/
...
...
@@ -851,7 +862,7 @@ _start:
/*-----------------------------------------------------------------------
*/
/
*
Enable
two
128
MB
cachable
regions
.
*/
/*-----------------------------------------------------------------------
*/
lis
r4
,
0x
8
000
lis
r4
,
0x
c
000
ori
r4
,
r4
,
0x0001
mticcr
r4
/*
instruction
cache
*/
isync
...
...
@@ -860,12 +871,34 @@ _start:
ori
r4
,
r4
,
0x0000
mtdccr
r4
/*
data
cache
*/
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
|| defined(CONFIG_405EX)
/*-----------------------------------------------------------------------
*/
/
*
Tune
the
speed
and
size
for
flash
CS0
*/
/*-----------------------------------------------------------------------
*/
bl
ext_bus_cntlr_init
#endif
#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
/
*
*
Boards
like
the
Kilauea
(
40
5
EX
)
don
't have OCM and can'
t
use
*
DCache
for
init
-
ram
.
So
setup
stack
here
directly
after
the
*
SDRAM
is
initialized
.
*/
lis
r1
,
CFG_INIT_RAM_ADDR
@
h
ori
r1
,
r1
,
CFG_INIT_SP_OFFSET
/*
set
up
the
stack
in
SDRAM
*/
li
r0
,
0
/*
Make
room
for
stack
frame
header
and
*/
stwu
r0
,
-
4
(
r1
)
/*
clear
final
stack
frame
so
that
*/
stwu
r0
,
-
4
(
r1
)
/*
stack
backtraces
terminate
cleanly
*/
/
*
*
Set
up
a
dummy
frame
to
store
reset
vector
as
return
address
.
*
this
causes
stack
underflow
to
reset
board
.
*/
stwu
r1
,
-
8
(
r1
)
/*
Save
back
chain
and
move
SP
*/
lis
r0
,
RESET_VECTOR
@
h
/*
Address
of
reset
vector
*/
ori
r0
,
r0
,
RESET_VECTOR
@
l
stwu
r1
,
-
8
(
r1
)
/*
Save
back
chain
and
move
SP
*/
stw
r0
,
+
12
(
r1
)
/*
Save
return
addr
(
underflow
vect
)
*/
#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
#if defined(CONFIG_405EP)
/*-----------------------------------------------------------------------
*/
...
...
@@ -983,7 +1016,7 @@ start_ram:
ori
r4
,
r4
,
0xa000
mtdcr
ebccfgd
,
r4
/
*
turn
on
data
c
h
ache
for
this
region
*/
/
*
turn
on
data
cache
for
this
region
*/
lis
r4
,
0x0080
mtdccr
r4
...
...
@@ -1049,30 +1082,6 @@ start_ram:
/*-----------------------------------------------------------------------
*/
bl
sdram_init
/
*
*
Setup
temporary
stack
pointer
only
for
boards
*
that
do
not
use
SDRAM
SPD
I2C
stuff
since
it
*
is
already
initialized
to
use
DCACHE
or
OCM
*
stacks
.
*/
#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
lis
r1
,
CFG_INIT_RAM_ADDR
@
h
ori
r1
,
r1
,
CFG_INIT_SP_OFFSET
/*
set
up
the
stack
in
SDRAM
*/
li
r0
,
0
/*
Make
room
for
stack
frame
header
and
*/
stwu
r0
,
-
4
(
r1
)
/*
clear
final
stack
frame
so
that
*/
stwu
r0
,
-
4
(
r1
)
/*
stack
backtraces
terminate
cleanly
*/
/
*
*
Set
up
a
dummy
frame
to
store
reset
vector
as
return
address
.
*
this
causes
stack
underflow
to
reset
board
.
*/
stwu
r1
,
-
8
(
r1
)
/*
Save
back
chain
and
move
SP
*/
lis
r0
,
RESET_VECTOR
@
h
/*
Address
of
reset
vector
*/
ori
r0
,
r0
,
RESET_VECTOR
@
l
stwu
r1
,
-
8
(
r1
)
/*
Save
back
chain
and
move
SP
*/
stw
r0
,
+
12
(
r1
)
/*
Save
return
addr
(
underflow
vect
)
*/
#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
#ifdef CONFIG_NAND_SPL
bl
nand_boot
/*
will
not
return
*/
#else
...
...
@@ -1273,7 +1282,7 @@ icache_enable:
bl
invalidate_icache
mtlr
r8
isync
addis
r3
,
r0
,
0x
8
000
/*
set
bit
0
*/
addis
r3
,
r0
,
0x
c
000
/*
set
bit
0
*/
mticcr
r3
blr
...
...
cpu/ppc4xx/vecnum.h
浏览文件 @
dbbd1257
...
...
@@ -270,6 +270,110 @@
#define VECNUM_EIR3 30
/* External interrupt 3 */
#define VECNUM_EIR4 31
/* External interrupt 4 */
#elif defined(CONFIG_405EX)
/* UIC 0 */
#define VECNUM_U0 00
#define VECNUM_U1 01
#define VECNUM_IIC0 02
#define VECNUM_PKA 03
#define VECNUM_TRNG 04
#define VECNUM_EBM 05
#define VECNUM_BGI 06
#define VECNUM_IIC1 07
#define VECNUM_SPI 08
#define VECNUM_EIR0 09
#define VECNUM_MTE 10
/* MAL Tx EOB */
#define VECNUM_MRE 11
/* MAL Rx EOB */
#define VECNUM_DMA0 12
#define VECNUM_DMA1 13
#define VECNUM_DMA2 14
#define VECNUM_DMA3 15
#define VECNUM_PCIE0AL 16
#define VECNUM_PCIE0VPD 17
#define VECNUM_RPCIE0HRST 18
#define VECNUM_FPCIE0HRST 19
#define VECNUM_PCIE0TCR 20
#define VECNUM_PCIEMSI0 21
#define VECNUM_PCIEMSI1 22
#define VECNUM_SECURITY 23
#define VECNUM_ETH0 24
#define VECNUM_ETH1 25
#define VECNUM_PCIEMSI2 26
#define VECNUM_EIR4 27
#define VECNUM_UIC2NC 28
#define VECNUM_UIC2C 29
#define VECNUM_UIC1NC 30
#define VECNUM_UIC1C 31
/* UIC 1 */
#define VECNUM_MS (32 + 00)
/* MAL SERR */
#define VECNUM_TXDE (32 + 01)
/* MAL TXDE */
#define VECNUM_RXDE (32 + 02)
/* MAL RXDE */
#define VECNUM_PCIE0BMVC0 (32 + 03)
#define VECNUM_PCIE0DCRERR (32 + 04)
#define VECNUM_EBC (32 + 05)
#define VECNUM_NDFC (32 + 06)
#define VECNUM_PCEI1DCRERR (32 + 07)
#define VECNUM_CT8 (32 + 08)
#define VECNUM_CT9 (32 + 09)
#define VECNUM_PCIE1AL (32 + 10)
#define VECNUM_PCIE1VPD (32 + 11)
#define VECNUM_RPCE1HRST (32 + 12)
#define VECNUM_FPCE1HRST (32 + 13)
#define VECNUM_PCIE1TCR (32 + 14)
#define VECNUM_PCIE1VC0 (32 + 15)
#define VECNUM_CT3 (32 + 16)
#define VECNUM_CT4 (32 + 17)
#define VECNUM_EIR7 (32 + 18)
#define VECNUM_EIR8 (32 + 19)
#define VECNUM_EIR9 (32 + 20)
#define VECNUM_CT5 (32 + 21)
#define VECNUM_CT6 (32 + 22)
#define VECNUM_CT7 (32 + 23)
#define VECNUM_SROM (32 + 24)
/* SERIAL ROM */
#define VECNUM_GPTDECPULS (32 + 25)
/* GPT Decrement pulse */
#define VECNUM_EIR2 (32 + 26)
#define VECNUM_EIR5 (32 + 27)
#define VECNUM_EIR6 (32 + 28)
#define VECNUM_EMAC0WAKE (32 + 29)
#define VECNUM_EIR1 (32 + 30)
#define VECNUM_EMAC1WAKE (32 + 31)
/* UIC 2 */
#define VECNUM_PCIE0INTA (64 + 00)
/* PCIE0 INTA */
#define VECNUM_PCIE0INTB (64 + 01)
/* PCIE0 INTB */
#define VECNUM_PCIE0INTC (64 + 02)
/* PCIE0 INTC */
#define VECNUM_PCIE0INTD (64 + 03)
/* PCIE0 INTD */
#define VECNUM_EIR3 (64 + 04)
/* External IRQ 3 */
#define VECNUM_DDRMCUE (64 + 05)
#define VECNUM_DDRMCCE (64 + 06)
#define VECNUM_MALINTCOATX0 (64 + 07)
/* Interrupt coalecence TX0 */
#define VECNUM_MALINTCOATX1 (64 + 08)
/* Interrupt coalecence TX1 */
#define VECNUM_MALINTCOARX0 (64 + 09)
/* Interrupt coalecence RX0 */
#define VECNUM_MALINTCOARX1 (64 + 10)
/* Interrupt coalecence RX1 */
#define VECNUM_PCIE1INTA (64 + 11)
/* PCIE0 INTA */
#define VECNUM_PCIE1INTB (64 + 12)
/* PCIE0 INTB */
#define VECNUM_PCIE1INTC (64 + 13)
/* PCIE0 INTC */
#define VECNUM_PCIE1INTD (64 + 14)
/* PCIE0 INTD */
#define VECNUM_RPCIEMSI2 (64 + 15)
/* MSI level 2 */
#define VECNUM_PCIEMSI3 (64 + 16)
/* MSI level 2 */
#define VECNUM_PCIEMSI4 (64 + 17)
/* MSI level 2 */
#define VECNUM_PCIEMSI5 (64 + 18)
/* MSI level 2 */
#define VECNUM_PCIEMSI6 (64 + 19)
/* MSI level 2 */
#define VECNUM_PCIEMSI7 (64 + 20)
/* MSI level 2 */
#define VECNUM_PCIEMSI8 (64 + 21)
/* MSI level 2 */
#define VECNUM_PCIEMSI9 (64 + 22)
/* MSI level 2 */
#define VECNUM_PCIEMSI10 (64 + 23)
/* MSI level 2 */
#define VECNUM_PCIEMSI11 (64 + 24)
/* MSI level 2 */
#define VECNUM_PCIEMSI12 (64 + 25)
/* MSI level 2 */
#define VECNUM_PCIEMSI13 (64 + 26)
/* MSI level 2 */
#define VECNUM_PCIEMSI14 (64 + 27)
/* MSI level 2 */
#define VECNUM_PCIEMSI15 (64 + 28)
/* MSI level 2 */
#define VECNUM_PLB4XAHB (64 + 29)
/* PLBxAHB bridge */
#define VECNUM_USBWAKE (64 + 30)
/* USB wakup */
#define VECNUM_USBOTG (64 + 31)
/* USB OTG */
#else
/* !CONFIG_405EZ */
#define VECNUM_U0 0
/* UART0 */
...
...
include/405_mal.h
浏览文件 @
dbbd1257
...
...
@@ -92,7 +92,9 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020
...
...
include/4xx_i2c.h
浏览文件 @
dbbd1257
...
...
@@ -43,7 +43,7 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
#elif defined(CONFIG_440)
#elif defined(CONFIG_440)
|| defined(CONFIG_405EX)
/* all remaining 440 variants */
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
#else
...
...
include/asm-ppc/processor.h
浏览文件 @
dbbd1257
...
...
@@ -765,6 +765,10 @@
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
#define PVR_405EXR1_RA 0x12911473
/* 405EXr rev A with Security */
#define PVR_405EXR2_RA 0x12911471
/* 405EXr rev A without Security */
#define PVR_405EX1_RA 0x12911477
/* 405EX rev A with Security */
#define PVR_405EX2_RA 0x12911475
/* 405EX rev A without Security */
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
...
...
include/asm-ppc/u-boot.h
浏览文件 @
dbbd1257
...
...
@@ -84,6 +84,7 @@ typedef struct bd_info {
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \
defined(CONFIG_440)
unsigned
char
bi_s_version
[
4
];
/* Version of this structure */
unsigned
char
bi_r_version
[
32
];
/* Version of the ROM (AMCC) */
...
...
include/common.h
浏览文件 @
dbbd1257
...
...
@@ -266,7 +266,7 @@ void pciinfo (int, int);
int
pci_pre_init
(
struct
pci_controller
*
);
#endif
#if defined(CONFIG_PCI) &&
defined(CONFIG_440
)
#if defined(CONFIG_PCI) &&
(defined(CONFIG_440) || defined(CONFIG_405EX)
)
# if defined(CFG_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
);
# endif
...
...
@@ -274,7 +274,7 @@ void pciinfo (int, int);
void
pci_master_init
(
struct
pci_controller
*
);
# endif
int
is_pci_host
(
struct
pci_controller
*
);
#if defined(CONFIG_440SPE)
#if defined(CONFIG_440SPE)
|| defined(CONFIG_405EX)
void
pcie_setup_hoses
(
int
busno
);
#endif
#endif
...
...
include/ppc405.h
浏览文件 @
dbbd1257
此差异已折叠。
点击以展开。
include/ppc440.h
浏览文件 @
dbbd1257
...
...
@@ -3345,7 +3345,7 @@ typedef struct {
unsigned
long
freqTmrClk
;
unsigned
long
freqPLB
;
unsigned
long
freqOPB
;
unsigned
long
freqE
PB
;
unsigned
long
freqE
BC
;
unsigned
long
freqPCI
;
#ifdef CONFIG_440SPE
unsigned
long
freqDDR
;
...
...
include/ppc4xx_enet.h
浏览文件 @
dbbd1257
...
...
@@ -146,11 +146,12 @@ typedef struct emac_4xx_hw_st {
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
/*ZMII Bridge Register addresses */
/*
ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
...
...
@@ -202,6 +203,8 @@ typedef struct emac_4xx_hw_st {
/* RGMII Register Addresses */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
#elif defined(CONFIG_405EX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00)
#else
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
#endif
...
...
@@ -223,7 +226,8 @@ typedef struct emac_4xx_hw_st {
#define RGMII_SSR_SP_100MBPS (0x02)
#define RGMII_SSR_SP_1000MBPS (0x04)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define RGMII_SSR_V(__x) ((__x) * 8)
#else
#define RGMII_SSR_V(__x) ((__x -2) * 8)
...
...
@@ -304,7 +308,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
#else
#if defined(CONFIG_405EZ)
#if defined(CONFIG_405EZ)
|| defined(CONFIG_405EX)
#define EMAC_BASE 0xEF600900
#else
#define EMAC_BASE 0xEF600800
...
...
@@ -338,7 +342,8 @@ typedef struct emac_4xx_hw_st {
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
...
...
include/serial.h
浏览文件 @
dbbd1257
...
...
@@ -22,8 +22,9 @@ extern struct serial_device serial_smc_device;
extern
struct
serial_device
serial_scc_device
;
extern
struct
serial_device
*
default_serial_console
(
void
);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
defined(CONFIG_MPC5xxx)
extern
struct
serial_device
serial0_device
;
extern
struct
serial_device
serial1_device
;
#if defined(CFG_NS16550_SERIAL)
...
...
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