- 05 12月, 2013 1 次提交
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由 Hardik Patel 提交于
Signed-off-by: NHardik Patel <hardik.patel@volansystech.com>
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- 04 12月, 2013 1 次提交
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由 SRICHARAN R 提交于
When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: NSricharan R <r.sricharan@ti.com>
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- 15 10月, 2013 1 次提交
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由 Dan Murphy 提交于
OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory part. The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron so the timings needs to be updated Signed-off-by: NDan Murphy <dmurphy@ti.com>
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- 28 8月, 2013 1 次提交
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由 Lubomir Popov 提交于
OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. This memory has 4Gb x 2CS = 8Gb configuration. Add configuration for runtime calculation and precalculated cases. Patch is based on a draft Lubomir's patch [1]. [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.htmlSigned-off-by: NLubomir Popov <lpopov@mm-sol.com> [taras@ti.com: cleaned up patch and fixed precalculated values] Signed-off-by: NTaras Kondratiuk <taras@ti.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 11 3月, 2013 2 次提交
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由 Lokesh Vutla 提交于
DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NR Sricharan <r.sricharan@ti.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Lokesh Vutla 提交于
Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: NR Sricharan <r.sricharan@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@ti.com>
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- 07 7月, 2012 2 次提交
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由 SRICHARAN R 提交于
The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 Lokesh Vutla 提交于
Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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- 15 5月, 2012 1 次提交
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由 SRICHARAN R 提交于
The OMAP5 silicon has new DDR PHY design, which includes a external PHY as well. So configuring the ext PHY parameters here. Also the EMIF timimg registers and a couple of DDR mode registers needs to be updated based on the testing from the actual silicon. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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- 16 11月, 2011 1 次提交
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由 Sricharan 提交于
Add the emif configurations required for omap5 soc.Add the correct ddr part configurations required for omap5 evm board. EDB8164B3PH from ELPIDA is the part used on the board. Also changes are done to retain some part of the code common for OMAP4/5 and keep only the remaining in the Soc specific directories. Signed-off-by: Nsricharan <r.sricharan@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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- 13 9月, 2011 1 次提交
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由 Aneesh V 提交于
SDRAM init was not working on ES1.0 due to a programming error. A pointer that was passed by value to a function was set in function emif_get_device_details(), but the effect wouldn't be seen in the calling function. The issue came out while testing for ES1.0 because ES1.0 doesn't have any SDRAM chips connected to CS1 Signed-off-by: NAneesh V <aneesh@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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- 03 8月, 2011 2 次提交
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由 Aneesh V 提交于
Calculate EMIF register values based on AC timing parameters from the SDRAM datasheet and the DDR frequency rather than using the hard-coded values. For a new board the user doen't have to go through the tedious process of calculating the register values. Instead, just provide the AC timings from the device data sheet as input and the driver will automatically calculate the register values. Signed-off-by: NAneesh V <aneesh@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Aneesh V 提交于
Add support for the SDRAM controller (EMIF). Signed-off-by: NAneesh V <aneesh@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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