Signed-off-by: NHardik Patel <hardik.patel@volansystech.com>

Certain EFUSE settings were recommended for the first
four lots of OMAP5 ES1.0 silicon. These are not applicable
for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings.
Reported-by: NGriffis, Brad <bgriffis@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Adds the necessary PRCM and Control register information for
SATA on DRA7xx.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Add platform glue logic for the SATA controller.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Adds the necessary PRCM and Control register information for
SATA on OMAP5.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is
a driver for the Pipe3 PHY.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified.  This has been tested
on AM335x GP EVM and Beaglebone White.

[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: NTom Rini <trini@ti.com>
Tested-by: NMatt Porter <matt.porter@linaro.org>

The struct incorrectly referenced SMPS1 for all three power
domains. Fixed this by using SMPS2 and SMPS5 as appropriate.

Add some comments and choose voltage values that correspond
to voltage selection codes.
Signed-off-by: NLubomir Popov <l-popov@ti.com>

Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

add common phy reset code into a common function.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Jens Scharsig <esw@bus-elektronik.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Markus Hubig <mhubig@imko.de>
Acked-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Enable Atmel sama5d3xek boart spl boot support, which can load u-boot
from SD card with FAT file system.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

As the DBGU and PIT has its own ID on sama5d3 SoC, while not share
with SYS ID. So, correct them.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The SAMA5D36 chip is the superset product of SAMA5D3x family.

For detail information please refer to:
  http://www.atmel.com/Microsite/sama5d3/default.aspxSigned-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

As
http://www.denx.de/wiki/view/U-Boot/DesignPrinciples#2_Keep_it_Fast
states:
"Initialize devices only when they are needed within U-Boot"

enable the RTC32K OSC only, if CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is
enabled. Enable this in ti_am335x_common.h, so all boards in mainline
should work as before.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>

TZ_DDR_RAM on reset is in secure mode.
Since uboot and linux runs in full
TZ privilege secure mode, no need
to set DDR trustzone to non-secure.
Signed-off-by: NRadhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

In case where ps-ddr is not used, do not remap
OCM to high address and keep it from 0x0.
Linux SMP requires to have memory at 0x0.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Convert versatile to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert tegra to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert socfpga to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert mx25 to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert highbank to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

There is a board-specific portion for calling watchdog enable itself, in
main U-Boot.
Signed-off-by: NTom Rini <trini@ti.com>

Create a common header file for the RTC IP block that is shared between
davinci and am33xx.
Signed-off-by: NTom Rini <trini@ti.com>

This patch moves S5PC, EXYNOS specific directory entries
from the toplevel Makefile to arch/arm/cpu/armv7/Makefile
using Kbuild descending feature.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>

This patch moves OMAP specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/armv7/Makefile using Kbuild descending feature.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>

This patch moves Tegra specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/*/Makefile using Kbuild descending feature.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <TWarren@nvidia.com>

In case the board detected sufficient voltage for battery boot,
make sure the DCDC converter is ON and the board is not running
only from linregs, otherwise an instability will be observed.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

setup_wdog macro is not used anywhere, so just remove it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Enable L2 cache for improving the system performance.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Note1:
In arch/arm/cpu/arm926ejs/spear/Makefile
START := start.o
was changed
extra-$(CONFIG_SPL_BUILD) := start.o
because spear/start.o is only used for SPL.

Note2:
START := start.o
was missing from arch/arm/cpu/arm926ejs/mxs/Makefile.
This commit simply adds
extra-$(CONFIG_SPL_BUILD) := start.o
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.

The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: NDan Murphy <dmurphy@ti.com>

Add the prcm registers and the bit definitions to enable the
USB SS port of the OMAP5 device.
Signed-off-by: NDan Murphy <dmurphy@ti.com>

Adding methods to turn on/off power to USB3.0 type PHY
as and when required by the controller.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>