- 25 7月, 2019 1 次提交
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由 Weijie Gao 提交于
This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR and SPI-NAND flashes. Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com> [jagan: squash MAINTAINERS file] Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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- 22 7月, 2019 1 次提交
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由 Ashish Kumar 提交于
mt35xu512aba and mt35xu02g suports Single I/O and OCTAL I/O also enable use of SPI_NOR_4B_OPCODES. These flashes are tested on LX2160ARDB and LS1028ARDB respectively Signed-off-by: NKuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com> [jagan: suffix 'ba' on part name and update commit message] Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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- 18 7月, 2019 6 次提交
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由 Ashish Kumar 提交于
mt25qu512a is rebranded after its spinoff from STM, so it is different only in term of extended jedec ID, initial JEDEC id is same as that of n25q512a.In order to avoid any confussion with respect to name new entry is added. This flash is tested for Single I/O mode on LS1046FRWY although it also support QUAD I/O. Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Bhargav Shah 提交于
This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework. The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board. This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources. Signed-off-by: NBhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Anup Patel 提交于
Most DM based SPI host controller drivers use SPI_XFER_BEGIN and SPI_XFER_END flags to enable/disable slave chip select. This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when MMC command is send at start and pass SPI_XFER_END flag using a dummy transfer (of bitlen = 0) at the end of MMC command. Suggested-by: NJagan Teki <jagan@amarulasolutions.com> Signed-off-by: NAnup Patel <anup.patel@wdc.com> Tested-by: NSagar Kadam <sagar.kadam@sifive.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Thomas Schaefer 提交于
Use readl_poll_timeout instead of explicit calculation Signed-off-by: NThomas Schaefer <thomas.schaefer@kontron.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Thomas Schaefer 提交于
During QSPI reads, current is_controller_busy function sporadically fails with -ETIMEDOUT due to fixed number of 5 test loops. Using timer functions to wait 1000 us instead will fix this. Signed-off-by: NThomas Schaefer <thomas.schaefer@kontron.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Ye Li 提交于
When slave drivers don't set the max_read_size, the spi-mem should directly use data.nbytes and not limit to any size. But current logic will limit to the max_write_size. Signed-off-by: NYe Li <ye.li@nxp.com> Acked-by: NVignesh Raghavendra <vigneshr@ti.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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- 16 7月, 2019 29 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi由 Tom Rini 提交于
- Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
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由 Andre Przywara 提交于
So far USB was not enabled for the Allwinner H6 boards, as the PHY driver was not ready and the clock gates were missing. Since this is now fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for all existing H6 boards. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jernej Skrabec 提交于
Add some basic line delay values to be used with DDR3 DRAM chips on some H6 TV boxes. Taken from a register dump after boot0 initialised the DRAM. Put them as the default delay values for DDR3 DRAM until we know better. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
At the moment the H6 DRAM driver only supports LPDDR3 DRAM. Extend the driver to cover DDR3 DRAM as well. The changes are partly motivated by looking at the ZynqMP register documentation, partly by looking at register dumps after boot0/libdram has initialised the controller. Many thanks to Jernej for contributing some fixes! Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The DRAM controller manual suggests to first program the PHY initialisation parameters to the PHY_PIR register, and then set bit 0 to trigger the initialisation. This is also used in boot0. Follow this recommendation by setting bit 0 in a separate step. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Using memcpy() is, however tempting, not a good idea: It depends on the specific implementation of memcpy, also lacks barriers. In this particular case the first registers were written using 64-bit writes, and the last register using four separate single-byte writes. Replace the memcpy with a proper loop using the writel() accessor. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Radu Pirea 提交于
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: NRadu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Radu Pirea 提交于
If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: NRadu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Grygorii Strashko 提交于
Enable TI K3 AM65x CPSW NUSS driver. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Grygorii Strashko 提交于
Add mcu cpsw nuss pinmux and phy defs required by cpsw. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Grygorii Strashko 提交于
Add mcu cpsw and its components along with scm_conf node to have ethernet functional. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Keerthy 提交于
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Keerthy 提交于
Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Yinbo Zhu 提交于
This patch is to use block layer to read from mmc in cortina Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Horatiu Vultur 提交于
Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alex Marginean 提交于
A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alex Marginean 提交于
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Horatiu Vultur 提交于
When serdes configuration was written in hardware there was a delay of 100ms to be sure that configuration was written. But the delay is not needed because already the function serdes_write it is checking that the operation finished. Therefore remove the mdelay. This improves the speed of configuring the network driver. Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Trent Piepho 提交于
The code block reading the DT property for the clock output control was before the phy's DT node pointer was set, so it could never work. Move it after the node pointer is set. Also store the unsigned 32-bit property into an unsigned value, not a signed value, as the former will cause a problem if value overflows. For instance, if one were to add 0xffffffff as a code to mean the clock output should be turned off. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NTrent Piepho <tpiepho@impinj.com> Reviewed-by: NGrygorii Strashko <grygorii.strashko@ti.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Trent Piepho 提交于
When not using DM_ETH, these PHY settings are programmed with default values hardcoded into the driver. When using DM_ETH, they should come from the device tree. However, if the device tree does not have the properties, the driver will silent use -1. Which is entirely out of range, programs nonsense into the PHY's registers, and does not work. Change this to use the same defaults as non-DM_ETH if the device tree is lacking the properties. As an alternative, the kernel driver for the phy will display an error message and fail if the device tree is lacking. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NTrent Piepho <tpiepho@impinj.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Trent Piepho 提交于
These are standard across gigabit phys. These mostly extend the auto-negotiation information with gigabit fields. Signed-off-by: NTrent Piepho <tpiepho@impinj.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Trent Piepho 提交于
Share the code that prints out a register field with the function that prints out the "special" fields. There were two arrays the register dump list, one with reg number and name, another with a pointer to the field table and the table size. These two arrays had have each entry match what register is referred to. Combine them into just one table. Now they can't not match and there is just one table. Add some missing consts to pointers to string literals. The dump code was ignoring the regno field in the description table and assuming register 0 was at index 0, etc. Have it use the field. Change reg > max+1 into reg >= max, which doesn't fail if max+1 could overflow, besides just making more sense. Signed-off-by: NTrent Piepho <tpiepho@impinj.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 15 7月, 2019 3 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-mmc由 Tom Rini 提交于
- mmc spi driver model support - drop mmc_spi command - enhanced Strobe mmc HS400 support - minor mmc bug/fixes and optimization - omap hsmmc and mvbeu update - sdhci card detect support
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由 Marcus Cooper 提交于
The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot, 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a dual colour LED and an optical S/PDIF connector. Linux commit details about the sun8i-h3-beelink-x2.dts sync: "ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2" (sha1: cc4bddade114b696ab27c1a77cfc7040151306da) Signed-off-by: NMarcus Cooper <codekipper@gmail.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The choice of the SPL_TEXT_BASE is not really a decision that should be specified by each board's defconfig, as this setting is actually dictated by the SoC's memory map and the BootROM behaviour. To make this obvious and reduce the clutter in the defconfig files, let's specify the SoC constraints in the Kconfig stanza. This allows us to remove these lines from the defconfig files again. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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