提交 c2df9b49 编写于 作者: T Trent Piepho 提交者: Joe Hershberger

net: phy: ti: Use default values for tx/rx delay and fifo size

When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver.  When using DM_ETH, they should come
from the device tree.  However, if the device tree does not have the
properties, the driver will silent use -1.  Which is entirely out of
range, programs nonsense into the PHY's registers, and does not work.

Change this to use the same defaults as non-DM_ETH if the device tree is
lacking the properties.

As an alternative, the kernel driver for the phy will display an error
message and fail if the device tree is lacking.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NTrent Piepho <tpiepho@impinj.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
上级 95637868
......@@ -162,14 +162,14 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->rxctrl_strap_quirk = true;
dp83867->rx_id_delay = ofnode_read_u32_default(node,
"ti,rx-internal-delay",
-1);
DEFAULT_RX_ID_DELAY);
dp83867->tx_id_delay = ofnode_read_u32_default(node,
"ti,tx-internal-delay",
-1);
DEFAULT_TX_ID_DELAY);
dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
-1);
DEFAULT_FIFO_DEPTH);
if (ofnode_read_bool(node, "enet-phy-lane-swap"))
dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
......
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