The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.

Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits above the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: NTom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

SBC1 is SPI controller 1 on tegra30
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c

Some T30 tables needed whitespace fixes due to checkpatch complaints.
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.
Signed-off-by: NTom Warren <twarren@nvidia.com>

These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.

This function adds a clean way to do so.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.
Signed-off-by: NTom Warren <twarren@nvidia.com>

In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common.  This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Correct this warning seen by Albert:

ap20.c:44:18: warning: array subscript is above array bounds

There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This is needed for upcoming Toradex Colibri T20 upstream support.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Most boards will want to enable a UART early. This function provides
that feature in Tegra architecture code so the code does not need to be
copied on every board.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This adds most of the clock functions required by board and driver code:

-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control

These functions are plumbed in as required.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NTom Warren <twarren@nvidia.com>

Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the
code now deals with both PLL clocks and source clocks.

This also tidied up the assert() to match the one sent upstream, and fixes
an error in the PWM id.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NTom Warren <twarren@nvidia.com>

Commit 21726a7a "Add assert() for debug assertions" caused build
warnings for all tegra2 based boards:

clock.c:36:1: warning: "assert" redefined
In file included from clock.c:29:
include/common.h:144:1: warning: this is the location of the previous definition
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>

This adds functions to enable/disable clocks and reset to on-chip peripherals.
Signed-off-by: NSimon Glass <sjg@chromium.org>